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2.1. HLS AFU Design Example Software Requirements
2.2. Compiling and Simulating the HLS Component with the i++ Command
2.3. Generating a Platform Designer Container for the HLS Component
2.4. Generating the ASE Testbench
2.5. Running the ASE Testbench
2.6. Compiling the AF Bitstream
2.7. Loading AF Bitstream and Running the Host Application
5.1. Platform Designer Opens with an Error
5.2. The design unit was not found Error When Running the make sim Command
5.3. Verilog HDL Compilation Errors
5.4. Compilation Errors During ASE Testbench Generation
5.5. Incorrect Output During Simulation
5.6. AF Bitstream Compilation Fails
5.7. Verilog Files Not Found Errors
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2.4. Generating the ASE Testbench
After integrating the HLS component into an AFU, you might want to cosimulate the AFU in the Intel AFU Simulation Environment (ASE). Use this cosimulation to quickly confirm the functionality of your HLS component within the AFU.
If you want to skip co-simulating the AFU in the ASE and run the design on hardware, go to Compiling the AF Bitstream.
Before you co-simulate your AFU in the ASE, ensure that your ASE is configured according to the instructions in the Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide.
You must have a valid license for one of the supported simulators to use the ASE.
Ensure that your simulation software environment variables are set correctly:
- For Mentor ModelSim* SE* or Mentor Questa* Advanced Simulator:
$ export MTI_HOME=<path to ModelSim/Questa installation directory> $ export PATH=$MTI_HOME/linux_x86_64/:$MTI_HOME/bin/:$PATH
Refer to hls_afu/setup_ase.sh to automate these steps.
To generate the ASE testbench:
- Navigate to the root of your project (the hls_afu directory) and run this command:
$ afu_sim_setup --source hw/rtl/filelist.txt build_ase_dir/
- Navigate to build_ase_dir directory.
- Open Makefile and add the twentynm libraries to the gate level library as follows:
The twentynm libraries are highlighted in bold text.# Gate level libraries to add to simulation GLS_VERILOG_OPT = $(QUARTUS_HOME)/eda/sim_lib/altera_primitives.v GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/220model.v GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/sgate.v GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/altera_mf.v GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/altera_lnsim.sv GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/twentynm_atoms.v GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/mentor/twentynm_atoms_ncrypt.v
- Run the following commands:
$ make $ make sim
When you see the following message, you can build and run the host.
Take note of the export command in your make sim command output. You need this command to set your environment to run the host program. The export command is highlighted in the following output example:# [SIM] ASE lock file .ase_ready.pid written in work directory # [SIM] ** ATTENTION : BEFORE running the software application ** # [SIM] Set env(ASE_WORKDIR) in terminal where application will run (copy-and-paste) => # [SIM] $SHELL | Run: # [SIM] ---------+--------------------------------------------------- # [SIM] bash/zsh | export ASE_WORKDIR=/home/john/hls_afu/build_ase_dir/work # [SIM] tcsh/csh | setenv ASE_WORKDIR /home/john/hls_afu/build_ase_dir/work # [SIM] For any other $SHELL, consult your Linux administrator # [SIM] # [SIM] Ready for simulation... # [SIM] Press CTRL-C to close simulator...
Leave this terminal window open. This terminal window is referred to in later steps as the ASE terminal window.