Intel Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683633
Date 12/04/2020
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2. Introduction

This guide provides a brief introduction to the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA, abbreviated as Intel® PAC with Intel® Arria® 10 GX FPGA in this document. This guide provides the instructions to:
  • Install the OPAE software
  • Upgrade the Intel® PAC with Intel® Arria® 10 GX FPGA FIM and BMC firmware
  • Activate the security features on the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA platform
  • Load and run a loopback test and the hello_fpga basic design example in both non-virtualized and virtualized environments

The Acceleration Stack is a collection of software, firmware, and tools that allows both software and RTL developers to take advantage of the power of Intel® FPGAs. By offloading computationally intensive tasks to the FPGA, the acceleration platform frees the Intel® Xeon® processor for other critical processing tasks.

The Intel® PAC with Intel® Arria® 10 GX FPGA, an accelerator card, connects to the Intel® Xeon® processor through the PCIe* interface on the motherboard.

Figure 1. Overview of the Intel® PAC with Intel® Arria® 10 GX FPGA Platform Hardware and Software

To take advantage of the flexibility of the FPGA, you can reconfigure a predefined, partial reconfiguration (PR) region of the Intel® Arria® 10 GX FPGA at run time. You can design multiple AFUs to swap in and out of this PR region. The Open Programmable Acceleration Engine (OPAE) software running on the Intel® Xeon® processor handles all the user-facing details of the reconfiguration process.

Security and reconfiguration are some of the many utilities that the OPAE provides. The OPAE also provides libraries, drivers, and sample programs useful for AFU development.

To facilitate dynamically loading AFUs, the Acceleration Stack includes the following two components:
  • The FIM provides a framework to load AFUs on the Intel® PAC with Intel® Arria® 10 GX FPGA. The FIM also includes the PR regions for the AFUs and the IP necessary to authenticate them. The FIM contains the FPGA logic to support the accelerators, including the PCIe* IP core, the CCI-P fabric, the on-board DDR memory interfaces, and the FPGA Management Engine (FME). At power up, an on-board FPGA configuration flash containing the FIM bitstream image configures the FIM. The PR regions are empty until the OPAE software programs the AFU images. The FIM framework is fixed. The current release of the FIM for the Intel® PAC with Intel® Arria® 10 GX FPGA supports a single PR region.
  • The Acceleration Stack supports creation of AFU images with either RTL or OpenCL* design flows. An AFU image includes the AFU PR region bitstream and metadata that provides OPAE information on AFU characteristics and operational parameters. The current release supports dynamically swapping a single AFU image in a single PR region per installed Intel® FPGA PAC.
Figure 2.  Intel® Arria® 10 with a Single AFU PR Region

The AFU connects to the Intel® Xeon® processor through the CCI-P interface and then the PCIe* link. The Intel® PAC with Intel® Arria® 10 GX FPGA platform uses a simplified version of the CCI-P interface. For more information about the CCI-P interface, refer to the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual.

The AFU has access to two banks of private DDR4-SDRAM memory, totaling 8 GB. Each DDR4 memory bank interface has a standard Avalon® Memory-Mapped (Avalon-MM) interface. For more information about this interface, refer to the Avalon-MM Interface Specifications.

The Intel® PAC with Intel® Arria® 10 GX FPGA supports a single QSFP+ network port.

For more information about security, refer to Security User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA .

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