Intel Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683633
Date 12/04/2020
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Getting Started 4. Installing the OPAE Software Package 5. Identifying the Flash Image and BMC Firmware 6. Running FPGA Diagnostics 7. Running the OPAE in a Non-Virtualized Environment 8. Running the OPAE in a Virtualized Environment 9. Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA Archives 10. Document Revision History for Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA A. Updating the FIM and BMC Firmware B. Handling Graceful Thermal Shutdown C. FPGA Device Access Permission D. Memlock Limit E. Hugepage Settings F. Troubleshooting Frequently Asked Questions (FAQ) G. Documentation Available for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2.1 Release
1. About This Document x
1.1. Intended Audience 1.2. Acronym List 1.3. Acceleration Glossary
3. Getting Started x
3.1. Intel Acceleration Stack Hardware Features 3.2. System Requirements 3.3. Installing the Intel® PAC with Intel® Arria® 10 GX FPGA Card In the Host Machine 3.4. Installing the Intel Acceleration Stack
3.4. Installing the Intel Acceleration Stack x
3.4.1. Installing the Intel Acceleration Stack Runtime Package on the Host Machine 3.4.2. Installing the Intel Acceleration Stack Development Package on the Host Machine 3.4.3. Understanding the Extracted Intel® PAC with Intel® Arria® 10 GX FPGA Release Package
4. Installing the OPAE Software Package x
4.1. RHEL 7.6: Installing the OPAE Framework from Prebuilt Binaries (RPM) 4.2. Ubuntu: Installing the OPAE Framework from Prebuilt Binaries (deb) 4.3. (Optional) Building and Installing the OPAE Software from Source Code 4.4. Installing the OPAE PACSign
7. Running the OPAE in a Non-Virtualized Environment x
7.1. Loading an AFU Image into the FPGA 7.2. OPAE Sample Application Programs
7.2. OPAE Sample Application Programs x
7.2.1. Running the Hello FPGA Example
8. Running the OPAE in a Virtualized Environment x
8.1. Updating Settings Required for VFs 8.2. Configuring the VF Port on the Host 8.3. Running the Hello FPGA Example on Virtual Machine
8.3. Running the Hello FPGA Example on Virtual Machine x
8.3.1. Disconnecting the VF from the VM and Reconnecting to the PF
A. Updating the FIM and BMC Firmware x
A.1. Selecting the Correct Update Method
A.1. Selecting the Correct Update Method x
A.1.1. Updating FPGA Flash and BMC Firmware
F. Troubleshooting Frequently Asked Questions (FAQ) x
F.1. Why do I see a 'No Suitable slots found' message when running fpgaconf on my AFU image? F.2. How do I flash the FIM or program the AFU in a multicard system? F.3. Which environment variables are required? F.4. What actions do I take if I see the error message 'Error enumerating resources: no driver available'? F.5. Troubleshooting OPAE Installation on RHEL
1. About This Document
2. Introduction
3. Getting Started
4. Installing the OPAE Software Package
5. Identifying the Flash Image and BMC Firmware
6. Running FPGA Diagnostics
7. Running the OPAE in a Non-Virtualized Environment
8. Running the OPAE in a Virtualized Environment
9. Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA Archives
10. Document Revision History for Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
A. Updating the FIM and BMC Firmware
B. Handling Graceful Thermal Shutdown
C. FPGA Device Access Permission
D. Memlock Limit
E. Hugepage Settings
F. Troubleshooting Frequently Asked Questions (FAQ)
G. Documentation Available for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2.1 Release

6. Running FPGA Diagnostics

This section presents instructions on how to run the FPGA diagnostics by using the fpgabist utility. The current AFUs accepted are nlb_mode_3 and dma_afu, running fpgadiag and fpga_dma_test tests, respectively.
Note: If a flash is programmed with a root entry hash, you must ensure that the AFUs are signed with an appropriate root key and code signing key before running the FPGA diagnostics. For more information on signing, refer to Security User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA .
  1. Configure the number of system hugepages the FPGA fpgadiag utility requires: 
    sudo sh -c "echo 20 > /sys/kernel/mm/hugepages/hugepages-\ 
2048kB/nr_hugepages"
  2. Configure and run diagnostics with the NLB_3 AFU image. 
    sudo fpgabist $OPAE_PLATFORM_ROOT/hw/samples/nlb_mode_3/bin/\
nlb_mode_3_unsigned.gbs
    Sample partial output: 
    Cachelines Read_Count Write_Count Cache_Rd_Hit Cache_Wr_Hit Cache_Rd_Miss Cache_Wr_Miss   Eviction 'Clocks(@400 MHz)'   Rd_Bandwidth   Wr_Bandwidth
1024  480797340   488815296             0            0             0             0          0       1000021563      6.234 GB/s    6.256 GB/s

VH0_Rd_Count VH0_Wr_Count VH1_Rd_Count VH1_Wr_Count VL0_Rd_Count VL0_Wr_Count480797340        488815297                        0            0            0            0

Built-in Self-Test Completed.
  3. Configure and run diagnostics with the DMA AFU image. 
    sudo fpgabist $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/bin/dma_afu_unsigned.gbs
    Sample partial output: 
    Running test in HW mode
Buffer Verification Success!
Buffer Verification Success!
Running DDR sweep test
Allocated test buffer
Fill test buffer
DDR Sweep Host to FPGA
Measured bandwidth = 6616.881910 Megabytes/sec
Clear buffer
DDR Sweep FPGA to Host
Measured bandwidth = 6932.201347 Megabytes/sec
Verifying buffer.
Buffer Verification Success!
Finished Executing DMA Tests
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