Intel Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683633
Date 12/04/2020
Document Table of Contents

1.2. Acronym List

Acronym Expansion Description
AFU Accelerator Functional Unit Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.
AF Acceleration Function Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.
ASE AFU Simulation Environment

Co-simulation environment that allows you to use the same host application and AF in a simulation environment. ASE is part of the Intel Acceleration Stack for FPGAs. 

BIP Bitstream Authentication IP Performs integrity and authentication checks on a bitstream using ECDSA-256 and SHA2-256 and returns a pass or fail state to the TCM.
CCI-P Core Cache Interface CCI-P is the standard interface that enables communication with the host.
FIM FPGA Interface Manager

The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.

The FPGA Interface Manager (FIM) may also be referred to as BBS (Blue-Bits, Blue BitStream) in the Acceleration Stack installation directory tree and in source code comments.

The Accelerator Function (AF) interfaces with the FIM at run time.

FIU FPGA Interface Unit FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe* and AFU-side interfaces such as CCI-P.
FME FPGA Management Engine

Provides the following functions:

  • Thermal monitoring
  • Performance monitoring
  • Partial reconfiguration
  • Global errors
HSSI High-speed Serial Interface Reference to the multi-gigabit serial transceiver I/O in the FIM and the corresponding interface to the AFU.
IOMMU Input–Output Memory Management Unit

An IOMMU is a memory management unit that connects a Direct Memory Access (DMA) I/O bus to main memory. The IOMMU maps device-visible virtual addresses to physical addresses.

OPAE Open Programmable Acceleration Engine

The OPAE is a software framework for managing and accessing AFs. 

PR Partial Reconfiguration The ability to dynamically reconfigure a portion of an FPGA while the remaining FPGA design continues to function. The FPGA includes PR region. You can reprogram these regions at run time to implement different AFUs as system requirements dictate.
TCM Trusted Configuration Manager Receives all updates to the AFU/PR region, FIM, and BMC, then authenticates them using the BIP. Authenticated bitstreams are loaded to their appropriate destination.