Developer Guide

Contents

Partitioning Buffers Across Different Memory Types (Heterogeneous Memory)

The board support package for your FPGA board can assemble a global memory space consisting of different memory technologies (for example, DRAM or SRAM). The board support package designates one such memory (which might consist of multiple interfaces) as the default memory. All buffers reside in this heterogeneous memory.
To use the heterogeneous memory, perform the following steps to modify the code in your source file:
  1. Determine the names of global memory types available on your FPGA board using one of the following methods:
    • Refer to the board vendor's documentation for information.
    • Identify the index of the global memory type in the
      board_spec.xml
      file of your Custom Platform. The index starts at 0 and follows the order in which the global memory appears in the
      board_spec.xml
      . For example, the first global memory type in the XML file has an index 0, the second has an index 1, and so on. For more information, refer to
      global_mem
      in the
      Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit User Guide
      .
  2. To instruct the host to allocate buffer to a specific global memory type, insert the
    buffer_location
    <index>
    property in the accessor's property list.
    For example:
    ext::oneapi::accessor_property_list PL{ext::intel::buffer_location<2>}; accessor acc(buffer, cgh, read_only, PL);
Using the
buffer_location
<index>
property on BSPs with heterogeneous memory support in combination with read-only cache is an untested functionality and Intel does not guarantee its support.
If you do not specify the
buffer_location
property, the host allocates the buffer to the default memory type automatically. To determine the default memory type, consult the documentation provided by your board vendor. Alternatively, in the
board_spec.xml
file of your Custom Platform, search for the memory type that is defined first or has the attribute
default=1
assigned to it. For more information, refer to
Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit User Guide
.
Streams support is limited if the target FPGA is used in a FPGA board with heterogeneous memory. With SYCL streams, all work items write to the same stream buffer in parallel, so atomics are leveraged to ensure race conditions. Atomics support for boards that have heterogeneous memory is limited. For more information about atomics and streams, refer to SYCL specifications available at https://www.khronos.org/registry/SYCL/specs/sycl-2020-provisional.pdf and https://www.khronos.org/registry/SYCL/specs/sycl-1.2.1.pdf.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.