FPGA Optimization Guide for Intel® oneAPI Toolkits

Developer Guide

Contents

Reduce Kernel Area and Latency

The
[[intel::use_stall_enable_clusters]]
 attribute enables you to direct the
Intel® oneAPI
DPC++/C++
 Compiler
 to reduce the area and latency of your kernel. Reducing the latency does not have a large effect on loops that are pipelined, unless the number of iterations of the loop is very small.
Computations in an FPGA kernel are normally grouped into the following cluster types:
  • Stall-Free Clusters (SFC)
    : Allows simplification of signals within a cluster, but the FIFO queue at the end of the cluster is used to save intermediate results if the computation must stall. For more information about SFCs, refer to Clustering the Datapath.
  • Stall-Enable Clusters (SEC)
    : Saves area and cycles by removing the FIFO queue and passing the stall signals to each part of the computation. These extra signals may cause the f
    MAX
     to reduce. For more information, refer to Clustering the Datapath.
If you specify the
[[intel::use_stall_enable_clusters]]
 attribute on one or more kernels, the compiler might reduce the f
MAX
 of the generated FPGA bitstream, which may reduce performance on all kernels.
The
[[intel::use_stall_enable_clusters]]
 attribute is not applicable for designs that target the Intel® Stratix® 10 architecture unless the
-Xshyper-optimized-handshaking=off
 option is passed to your
dpcpp
 command.
Example
h.single_task<class KernelComputeStallFree>( [=]() [[intel::use_stall_enable_clusters]] {
  // The computations in this device kernel uses Stall Enable Clusters
  Work(accessor_vec_a, accessor_vec_b, accessor_res);
});
The compiler uses Stall-Enable Clusters for the kernel when possible. Some computations might not be stallable, so the compiler places them in a Stall-Free Cluster even if a Stall-Enable Cluster was requested.
For more information, refer to the FPGA tutorial sample “Stall Enable Clusters” listed in the Intel® oneAPI Samples Browser on Linux*/Windows* or GitHub.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.