FPGA Optimization Guide for Intel® oneAPI Toolkits

Developer Guide

Contents

Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits

Date
Release Version
Changes
August 2022
2022.3
  • Added a note about setting the
    safelen
     parameter with 0 or 1 in
    ivdep
     Attribute
    .
  • Added a note about applying the
    ivdep
     attribute to an array in
    ivdep
     Attribute
    .
  • Minor update to example code in
    max_interleaving
     Attribute
    .
  • Updated all images and made moderate updates in all topics in the
    Analyze the FPGA Early Image
     section.
  • Made minor updates in Pipes topic.
  • Updated
    Latency Controls (Beta)
     topic completely.
  • Added a note about using the
    buffer_location
    <index>
     on BSPs with heterogeneous memory support in combination with read-only cache in
    Partitioning Buffers Across Different Memory Types (Heterogeneous Memory)
    .
  • Revised the guidance in
    Timing Failures
    .
  • Made minor revisions in
    Zero-Copy Memory Access
     and
    Prepinning Memory
     topics.
  • Added the following new topics:
    • System of Tasks (
      task_sequence
      ) Extension
    • Task Functions
    • task_sequence
       Use Cases
April 2022
2022.2
  • Changed the document title
    Intel® oneAPI DPC++ FPGA Optimization Guide
     to
    FPGA Optimization Guide for Intel® oneAPI Toolkits
    .
  • Replaced all general references to DPC++ with SYCL.
  • Added new loop functions to the existing list in
    FPGA Loop Directives
    .
  • Added a new limitation and removed some existing limitations in
    Advantages and Limitations of Arbitrary Precision Data Types
    .
  • Replaced all references to https://hlslibs.org/ with a reference to the documentation at https://github.com/hlslibs/ac_types/blob/v3.7/pdfdocs/ac_datatypes_ref.pdf.
  • Made a minor update to the description in
    The
    pipe
     Class and its Use
    .
  • Modified all occurrences of
    [[cl::reqd_work_group_size(Z, Y, X)]]
     to
    [[sycl::reqd_work_group_size(Z, Y, X)]]
    .
    [[cl::reqd_work_group_size(Z, Y, X)]]
     is now deprecated.
  • Added the following new topics:
    • Control Hardware Implementation of the Supported Data Types and Math Functions (
      -Xsdsp-mode=
      <option>
      )
    • Latency Controls
December 2021
2022.1
  • Added new attributes to the existing list in
    FPGA Loop Directives
     and
    FPGA Optimization Flags
    .
  • Added the following new topics:
    • Global Control of Exit FIFO Latency of Stall-free Clusters (
      -Xssfc-exit-fifo-type=
      <value>
      )
    • nofusion
       Attribute
    • Enable the Read-Only Cache for Read-Only Accessors (
      -Xsread-only-cache-size=
      <N>
      )
    • Renamed
      hls_float
       data type to
      ap_float
      . Added support for the header files
      <sycl/ext/intel/ac_types/ap_float.hpp>
       and
      <sycl/ext/intel/ac_types/ap_float_math.hpp>
      . In a future release, the header files
      <sycl/ext/intel/ac_types/hls_float.hpp>
       and
      <sycl/ext/intel/ac_types/hls_float_math.hpp>
       will be removed.
    • Updated few limitations in
      Advantages and Limitations of Arbitrary Precision Data Types
      .
September 2021
2021.4
  • Changed all occurrences of the namespace
    sycl::ONEAPI::
     to
    sycl::ext::oneapi::
    .
  • Changed all occurrences of the namespace
    sycl::INTEL::
     to
    sycl::ext::intel::
    .
  • Changed all occurrences of the header
    #include <CL/sycl/INTEL/...>
     to
    #include <sycl/ext/intel/...>
    .
  • Changed
    clang++
     to
    dpcpp
    .
  • Changed all occurrences of
    [[intel::ii(n)]]
     to
    [[intel::initiation_interval(n)]]
    .
  • Minor update about the types of FIFOs reported in the
    System Viewer
    .
  • Added a note about multi-process execution in the installed FPGAs in
    Multi-Threaded Host Application
    .
  • Added an additional value
    on
     to
    #pragma fp contract(fast/off)
    .
  • Updated the code snippets in
    Specify Schedule F
    MAX
     Target for Kernels
     and
    Memory Attributes
    .
  • Modified the flag description for AC type in
    Variable-Precision Integer and Floating-Point Support
    .
  • Modified the list of limitations in
    Advantages and Limitations of Arbitrary Precision Data Types
    .
  • Added information about debugging in
    Declare the
    ac_int
     Data Type
    .
  • Added support for simulation flow.
  • Changed all occurrences of Mentor Graphics* to Siemens EDA*
    (formerly Mentor Graphics) .
  • Changed the
    noinit
     attribute to
    no_init
    .
  • Modified the description of
    [[intel::kernel_args_restrict]]
     attribute in
    Global Memory Accesses Optimization
    .
  • Replaced the flag
    -Xsffpcontract=<value>
     with
    -fp-model=
    <value>
     and updated its description in
    Reducing Floating-Point Rounding Operations
    .
  • Removed few limitations of shift register in
    Kernel Variable Accesses
    .
  • Added the following new topics:
    • Modify the Rounding Mode of Floating-point Operations (
      -Xsrounding=<rounding_type>
      )
    • Reduce Kernel Area and Latency
       (
      [[intel::use_stall_enable_clusters]]
       attribute)
    • Timing Failures
July 2021
2021.3
Bug fixes.
June 2021
2021.3
  • Added more information about streaming data using I/O pipes and faking I/O pipes in
    I/O Pipes
    .
  • Added description about the local memory function in
    Kernel Memory
    .
  • Added a new section to describe the global memory bandwidth use calculation in
    Global Memory Accesses Optimization
    .
  • In
    System Viewer
    , added description about the global memory view, changed the Graph Viewer report name to System Viewer, updated all images and made minor updates in the remaining part of the topic.
  • Updated the description and image in
    Schedule Viewer
    .
  • Updated most of the code snippets to reflect the latest coding practices.
  • Made minor updates to the description of
    ivdep
     Attribute
     and
    loop_coalesce
     Attribute
    .
  • Added MLABs to the description in
    Perform Kernel Computations Using Local or Private Memory
    .
  • Modified the description in
    Strategies for Inferring the Accumulator
     to remove references to the
    -Xsfp-relaxed
     flag.
  • Updated the compilation options in
    Variable-Precision Integer and Floating-Point Support
    .
  • Updated the limitations in
    Advantages and Limitations of Arbitrary Precision Data Types
    .
  • Merged
    Ignoring Dependencies Between Accessor Arguments
     topic with
    Global Memory Accesses Optimization
    .
  • Updated the list of attributes in
    FPGA Kernel Attributes
    .
  • Added the following new topics:
    • Shannonization to Improve F
      MAX
      /II
    • Simple Host-device Streaming
    • Buffered Host-device Streaming
    • N-Way Buffering
    • Optimize Inner Loop Throughput
    • Improve Loop Performance by Caching On-Chip Memory
    • FPGA Local Memory Function
    • Pipelining Loops in Non-task Kernels (
      -Xsauto-pipeline
      )
    • Pipe and Atomic Fence
    • Reducing Floating-Point Rounding Operations (
      -Xsffp-contract=fast
      )
    • FPGA Accessor Properties
  • Removed the following topics because the respective flags are now deprecated:
    • Relax the Order of Floating-Point Operations (
      -Xsfp-relaxed
      )
    • Reduce Floating-Point Rounding Operations (
      -Xsfpc
      )
  • Removed
    Tree Balancing
     and
    Rounding Operations
     topic from
    Optimize Floating-point Operation
    .
March 2021
2021.2
  • Updated the topic
    Cluster the Datapath
     completely including the diagrams.
  • Updated the dependency graph in
    Mapping Source Code Instructions to Hardware
    .
  • Updated
    Hyper-Optimized Handshaking Data Flow
     diagram in
    Handshaking Between Clusters
     topic.
  • Made minor updates in
    Executing Independent Operations Simultaneously
    .
  • Updated the topic
    Pipelining
     completed including the diagrams.
  • Added a note about the enablement of fast math operations for floating point operations in
    Data Types and Operations
    .
  • Updated the topic
    Access HLD FPGA Reports in JSON Format
     to include details about the Bottlenecks viewer.
  • Made minor update to a note in
    Specify Number of SIMD Work-Items
  • Added the following new topics:
    • Floating Point Optimizations
    • Floating Point Pragmas
    • Specify Schedule F
      MAX
       Target for Kernels
    • Bottlenecks Viewer
    • Loop Bottlenecks
    • Variable-Precision Integer and Floating-Point Support
    • Advantages and Limitations of Arbitrary Precision Data Types
    • Declare and Use the AC Data Types
    • Declare the
      ac_int
       Data Type
    • Declare the
      ac_fixed
       Data Type
    • Declare the
      ac_complex
       Data Type
    • Declare the
      hls_float
       Data Type
    • Conversion Rules for
      hls_float
    • Operations with Explicit Precision Controls
    • Comparison Operators
    • Additional
      hls_float
       Functions
    • Additional Data Types Provided by
      hls_float.hpp
December 2020
2021.1
First major release.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.