The Intel^® Quartus^® Prime Programmer allows you to program and configure Intel FPGA CPLD, FPGA, and configuration devices. After compiling your design, use the Intel^® Quartus^® Prime Programmer to program or configure your device, to test the functionality of the design on a circuit board.

Intel FPGA offers the free stand-alone Programmer, which has the same full functionality as the Intel^® Quartus^® Prime Programmer in the Intel^® Quartus^® Prime software. The stand-alone Programmer is useful when programming your devices with another workstation, so you do not need two full licenses. You can download the stand-alone Programmer from the Download Center on the Altera website.

The Intel^® Quartus^® Prime software can generate optional programming or configuration files in various formats that you can use with programming tools other than the Intel^® Quartus^® Prime Programmer. When you compile a design in the Intel^® Quartus^® Prime software, the Assembler automatically generates either a .sof or .pof. The Assembler also allows you to convert FPGA configuration files to programming files for configuration devices.

The Intel^® Quartus^® Prime Programmer window allows you to:

• Add your programming and configuration files.
• Specify programming options and hardware.
• Start the programming or configuration of the device.

To open the Programmer window, click Tools > Programmer. As you proceed through the programming flow, the Intel^® Quartus^® Prime Message window reports the status of each operation.

The Intel^® Quartus^® Prime Programmer supports the generation of encryption key programming files and encrypted configuration files for Intel FPGAs that support the design security feature. You can also use the Intel^® Quartus^® Prime Programmer to program the encryption key into the FPGA.

The project hash doesn't change for different builds of the Intel^® Quartus^® Prime software, or when you install a software patch. However, if you upgrade any IP with a different build or patch, the project hash changes.

To obtain the project hash value of a .sof programming file for a design targeted to Arria^® V, Stratix^® V, Cyclone^® V, and Intel^® MAX^® 10 devices, use the following command, which dumps out metadata information that includes the project hash.

quartus_cpf --info <sof-file-name>

File: cb_intosc.sof
        File CRC: 0x0000
        Creator: Quartus Prime Compiler
        Version 17.0.0 Internal Build 565 02/09/2017 SJ Standard Edition
        Comment: UNIX 
        Device: 5SGSMD5K2F40
        Data checksum: 0x02534E5A 
        JTAG usercode: 0x02534E5A 
        Project Hash:  0x556e737065636966696564

To obtain the project hash value of a .sof programming file for a design targeted to Intel^® Arria^® 10 devices, create a file named project_hash.tcl. In your file, copy and paste the following code:

############################################
## Begin project_hash.tcl
#
##
## @copyright Intel 2017
##
proc main_run {} {
global quartus
set qargs $quartus(args)
set nargs [llength $qargs]
load_package asm2
load_devices
set handle -1
set sof_file [lindex $qargs 0]
if [file exists $sof_file] {
set handle [open_sof $sof_file]
}
print "/metadata/0/project_hash"
if { $handle != -1 } {
close_handle $handle
}
}
#############################################
main_run
## End of project_hash.tcl
#############################################

Save the project_hash.tcl file in the same directory that contains your programming file, and type in the command line:

quartus_asm -t project_hash.tcl <sof-file>

The script prints the project hash value to the command line output.

Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 17.0.0 Build 594 04/18/2017 SJ Standard Edition
Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors.  Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Sat Apr 22 00:44:19 2017
Info: Command: quartus_asm -t project_hash.tcl one_and.sof
Info: Quartus(args): one_and.sof
Info: Using INI file /data/msandova/qmap/quartus.ini
0x16cc7e6773644d398b740451aa0b26e3
Info (23030): Evaluation of Tcl script project_hash.tcl was successful
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 1111 megabytes
Info: Processing ended: Sat Apr 22 00:44:27 2017
Info: Elapsed time: 00:00:08

For example, to store the FPGA data in configuration devices, you can convert the .sof data to another format, such as .pof, .hexout, .rbf, .rpd, or .jic, and then program the configuration device.

You can also configure multiple devices with an external host, such as a microprocessor or CPLD. For example, you can combine multiple .sof files into one .pof file. To save time in subsequent conversions, click Save Conversion Setup to save your conversion specifications in a Conversion Setup File (.cof). Click Open Conversion Setup Data to load your .cof setup in the Convert Programming Files dialog box.

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
	<output_filename>output_file.pof</output_filename>
	<n_pages>1</n_pages>
	<width>1</width>
	<mode>14</mode>
	<sof_data>
		<user_name>Page_0</user_name>
		<page_flags>1</page_flags>
		<bit0>
			<sof_filename>/users/jbrossar/template/output_files/template_test.sof</sof_filename> 
		</bit0>
	</sof_data>
	<version>7</version>
	<create_cvp_file>0</create_cvp_file>
	<create_hps_iocsr>0</create_hps_iocsr>
	<auto_create_rpd>0</auto_create_rpd>
	<options>
		<map_file>1</map_file>
	</options>
	<MAX10_device_options>
		<por>0</por>
		<io_pullup>1</io_pullup>
		<auto_reconfigure>1</auto_reconfigure>
		<isp_source>0</isp_source>
		<verify_protect>0</verify_protect>
		<epof>0</epof>
		<ufm_source>0</ufm_source>
	</MAX10_device_options>
	<advanced_options>
		<ignore_epcs_id_check>0</ignore_epcs_id_check>
		<ignore_condone_check>2</ignore_condone_check>
		<plc_adjustment>0</plc_adjustment>
		<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
		<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
		<bitslice_pre_padding>1</bitslice_pre_padding>
	</advanced_options>
</cof>

The Convert Programming File dialog box supports the following programming file generation and option for Partial Reconfiguration:

• Partial-Masked SRAM Object File (.pmsf) output file generation, with .msf and .sof as input files.
• .rbf for Partial Reconfiguration output file generation, with a .pmsf as the input file.
  Note: The .rbf for Partial Reconfiguration file is only for Partial Reconfiguration.
• Providing the Enable decompression during Partial Reconfiguration option to enable the option bit for bitstream decompression during Partial Reconfiguration, when converting a full design .sof to any supported file type.

You can turn on the Enable decompression during Partial Reconfiguration option in the SOF File Properties: Bitstream Encryption dialog box, which you can access from the Convert Programming File dialog box. This option is available when converting a .sof to any supported programming file types listed in Secondary Programming Files.

This option is hidden for other targeted devices that do not support Partial Reconfiguration. To view this option in the SOF File Properties: Bitstream Encryption dialog box, the .sof must be targeted on an Intel FPGA device that supports Partial Reconfiguration.

If you turn on the Compression option when generating the .rbf for Partial Reconfiguration, then you must turn on the Enable decompression during Partial Reconfiguration option.

Parallel and serial configuration devices do not support the JTAG interface. However, you can use a flash loader to program configuration devices in-system via the JTAG interface. You can use an FPGA as a bridge between the JTAG interface and the configuration device. The Intel^® Quartus^® Prime software supports parallel and serial flash loaders.

During JTAG debug operation, the JTAG command sent from the Intel^® Quartus^® Prime Programmer ignores and overrides most of the Partial Reconfiguration IP core interface signals (clk, pr_start, double_pr, data[], data_valid, and data_read).

You can view the status of Partial Reconfiguration operation in the messages box and the Progress bar in the Intel^® Quartus^® Prime Programmer. The PR_DONE, PR_ERROR, and CRC_ERROR signals will be monitored during PR operation and reported in the Messages box at the end of the operation.

The Intel^® Quartus^® Prime Programmer can detect the number of PR_DONE instruction(s) in plain or compressed PR bitstream and, therefore, can handle single or double PR cycle accordingly. However, only single PR cycle is supported for encrypted Partial Reconfiguration bitstream in JTAG debug mode (provided that the specified device is configured with the encrypted base bitstream which contains the PR IP core in the design).

Error (12897): Partial Reconfiguration status: Can't reset the PR megafunction. This issue occurred because the design was corrupted by an incompatible PR bitstream in the previous PR operation. You must reconfigure the device with a good design.