1.8. JTAG Debug Mode for Partial Reconfiguration
During JTAG debug operation, the JTAG command sent from the Intel® Quartus® Prime Programmer ignores and overrides most of the Partial Reconfiguration IP core interface signals (clk, pr_start, double_pr, data, data_valid, and data_read).
You can view the status of Partial Reconfiguration operation in the messages box and the Progress bar in the Intel® Quartus® Prime Programmer. The PR_DONE, PR_ERROR, and CRC_ERROR signals will be monitored during PR operation and reported in the Messages box at the end of the operation.
The Intel® Quartus® Prime Programmer can detect the number of PR_DONE instruction(s) in plain or compressed PR bitstream and, therefore, can handle single or double PR cycle accordingly. However, only single PR cycle is supported for encrypted Partial Reconfiguration bitstream in JTAG debug mode (provided that the specified device is configured with the encrypted base bitstream which contains the PR IP core in the design).
Error (12897): Partial Reconfiguration status: Can't reset the PR megafunction. This issue occurred because the design was corrupted by an incompatible PR bitstream in the previous PR operation. You must reconfigure the device with a good design.
Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
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