1. Programming Intel FPGA Devices

Intel® Quartus® Prime Standard Edition User Guide: Programmer

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ID 683528

Date 9/24/2018

Version 18.1

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Visible to Intel only — GUID: mwh1410385041468

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Document Table of Contents

Document Table of Contents x

1. Programming Intel FPGA Devices A. Intel® Quartus® Prime Standard Edition User Guides

1. Programming Intel FPGA Devices x

1.1. Programming Flow 1.2. Intel® Quartus® Prime Programmer Window 1.3. Programming and Configuration Modes 1.4. Design Security Keys 1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files 1.6. Convert Programming Files Dialog Box 1.7. Flash Loaders 1.8. JTAG Debug Mode for Partial Reconfiguration 1.9. Scripting Support 1.10. Programming Intel® FPGA Devices Revision History

1.1. Programming Flow x

1.1.1. Stand-Alone Intel® Quartus® Prime Programmer 1.1.2. Optional Programming or Configuration Files 1.1.3. Secondary Programming Files

1.2. Intel® Quartus® Prime Programmer Window x

1.2.1. Editing the Details of an Unknown Device 1.2.2. Setting Up the Hardware 1.2.3. Setting the JTAG Hardware 1.2.4. Using the JTAG Chain Debugger Tool

1.2.3. Setting the JTAG Hardware x

1.2.3.1. Running JTAG Daemon with Linux

1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files x

1.5.1. Obtaining Project Hash for Arria® V, Stratix® V, Cyclone® V and Intel® MAX® 10 Devices 1.5.2. Obtaining Project Hash for Intel® Arria® 10 Devices

1.6. Convert Programming Files Dialog Box x

1.6.1. Debugging Your Configuration 1.6.2. Converting Programming Files for Partial Reconfiguration

1.6.2. Converting Programming Files for Partial Reconfiguration x

1.6.2.1. Generating .pmsf using a .msf and a .sof 1.6.2.2. Generating a .rbf for Partial Reconfiguration from a .pmsf file 1.6.2.3. Enable Decompression During Partial Reconfiguration Option

1.8. JTAG Debug Mode for Partial Reconfiguration x

1.8.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode

1.9. Scripting Support x

1.9.1. The jtagconfig Debugging Tool 1.9.2. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File 1.9.3. Generating Raw Binary File for Partial Reconfiguration using a .pmsf

1. Programming Intel FPGA Devices

1.1. Programming Flow

1.1.1. Stand-Alone Intel® Quartus® Prime Programmer

1.1.2. Optional Programming or Configuration Files

1.1.3. Secondary Programming Files

1.2. Intel® Quartus® Prime Programmer Window

1.2.1. Editing the Details of an Unknown Device

1.2.2. Setting Up the Hardware

1.2.3. Setting the JTAG Hardware

1.2.3.1. Running JTAG Daemon with Linux

1.2.4. Using the JTAG Chain Debugger Tool

1.3. Programming and Configuration Modes

1.4. Design Security Keys

1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files

1.5.1. Obtaining Project Hash for Arria® V, Stratix® V, Cyclone® V and Intel® MAX® 10 Devices

1.5.2. Obtaining Project Hash for Intel® Arria® 10 Devices

1.6. Convert Programming Files Dialog Box

1.6.1. Debugging Your Configuration

1.6.2. Converting Programming Files for Partial Reconfiguration

1.6.2.1. Generating .pmsf using a .msf and a .sof

1.6.2.2. Generating a .rbf for Partial Reconfiguration from a .pmsf file

1.6.2.3. Enable Decompression During Partial Reconfiguration Option

1.7. Flash Loaders

1.8. JTAG Debug Mode for Partial Reconfiguration

1.8.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode

1.9. Scripting Support

1.9.1. The jtagconfig Debugging Tool

1.9.2. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File

1.9.3. Generating Raw Binary File for Partial Reconfiguration using a .pmsf

1.10. Programming Intel® FPGA Devices Revision History

A. Intel® Quartus® Prime Standard Edition User Guides

Visible to Intel only — GUID: mwh1410385041468

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