Intel® Quartus® Prime Standard Edition User Guide: Programmer

ID 683528
Date 9/24/2018
Document Table of Contents

1.1. Programming Flow

In the FPGA flow, device programming requires a fully compiled design that includes the programming or configuration files that the Assembler generates.

To program a device:

  1. Convert the programming or configuration file to target the configuration device and, optionally, create secondary programming files.
    Table 1.  Programming and Configuration File Format
    File Format FPGA CPLD Configuration Device Serial Configuration Device
    SRAM Object File (.sof) Yes
    Programmer Object File (.pof) Yes Yes Yes
    JEDEC JESD71 STAPL Format File (.jam) Yes Yes Yes
    Jam Byte Code File (.jbc) Yes Yes Yes
  2. In the Intel® Quartus® Prime Programmer, program and configure the FPGA, CPLD, or configuration device with the appropriate programming or configuration files.
The FPGA now contains the design that you specified in the Intel® Quartus® Prime project.