Intel® Quartus® Prime Standard Edition User Guide: Programmer

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ID 683528
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Programming Intel FPGA Devices A. Intel® Quartus® Prime Standard Edition User Guides
1. Programming Intel FPGA Devices x
1.1. Programming Flow 1.2. Intel® Quartus® Prime Programmer Window 1.3. Programming and Configuration Modes 1.4. Design Security Keys 1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files 1.6. Convert Programming Files Dialog Box 1.7. Flash Loaders 1.8. JTAG Debug Mode for Partial Reconfiguration 1.9. Scripting Support 1.10. Programming Intel® FPGA Devices Revision History
1.1. Programming Flow x
1.1.1. Stand-Alone Intel® Quartus® Prime Programmer 1.1.2. Optional Programming or Configuration Files 1.1.3. Secondary Programming Files
1.2. Intel® Quartus® Prime Programmer Window x
1.2.1. Editing the Details of an Unknown Device 1.2.2. Setting Up the Hardware 1.2.3. Setting the JTAG Hardware 1.2.4. Using the JTAG Chain Debugger Tool
1.2.3. Setting the JTAG Hardware x
1.2.3.1. Running JTAG Daemon with Linux
1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files x
1.5.1. Obtaining Project Hash for Arria® V, Stratix® V, Cyclone® V and Intel® MAX® 10 Devices 1.5.2. Obtaining Project Hash for Intel® Arria® 10 Devices
1.6. Convert Programming Files Dialog Box x
1.6.1. Debugging Your Configuration 1.6.2. Converting Programming Files for Partial Reconfiguration
1.6.2. Converting Programming Files for Partial Reconfiguration x
1.6.2.1. Generating .pmsf using a .msf and a .sof 1.6.2.2. Generating a .rbf for Partial Reconfiguration from a .pmsf file 1.6.2.3. Enable Decompression During Partial Reconfiguration Option
1.8. JTAG Debug Mode for Partial Reconfiguration x
1.8.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1.9. Scripting Support x
1.9.1. The jtagconfig Debugging Tool 1.9.2. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File 1.9.3. Generating Raw Binary File for Partial Reconfiguration using a .pmsf
1. Programming Intel FPGA Devices
A. Intel® Quartus® Prime Standard Edition User Guides

1.6.1. Debugging Your Configuration

Use the Advanced option in the Convert Programming Files dialog box to debug your configuration. You must choose the advanced settings that apply to your Intel FPGA device. You can direct the Intel® Quartus® Prime software to enable or disable an advanced option by turning the option on or off in the Advanced Options dialog box. When you change settings in the Advanced Options dialog box, the change affects .pof, .jic, .rpd, and .rbf files.

The following table lists the Advanced Options settings in more detail:

Table 6.  Advanced Options Settings
Option Setting Description
Disable EPCS ID check

FPGA skips the EPCS silicon ID verification.

Default setting is unavailable (EPCS ID check is enabled).

Applies to the single- and multi-device AS configuration modes on all FPGA devices.

Disable AS mode CONF_DONE error check

FPGA skips the CONF_DONE error check.

Default setting is unavailable (AS mode CONF_DONE error check is enabled).

Applies to single- and multi-device (AS) configuration modes on all FPGA devices.

The CONF_DONE error check is disabled by default for Stratix® V, Arria® V, and Cyclone® V devices for AS-PS multi device configuration mode.

Program Length Count adjustment

Specifies the offset you can apply to the computed PLC of the entire bitstream.

Default setting is 0. The value must be an integer.

Applies to single- and multi-device (AS) configuration modes on all FPGA devices.

Post-chain bitstream pad bytes

Specifies the number of pad bytes appended to the end of an entire bitstream.

Default value is set to 0 if the bitstream of the last device is uncompressed. Set to 2 if the bitstream of the last device is compressed.

Post-device bitstream pad bytes

Specifies the number of pad bytes appended to the end of the bitstream of a device.

Default value is 0. No negative integer.

Applies to all single-device configuration modes on all FPGA devices.

Bitslice padding value

Specifies the padding value used to prepare bitslice configuration bitstreams, such that all bitslice configuration chains simultaneously receive their final configuration data bit.

Default value is 1. Valid setting is 0 or 1.

Use only in 2, 4, and 8-bit PS configuration mode, when you use an EPC device with the decompression feature enabled.

Applies to all FPGA devices that support enhanced configuration devices.

The following table lists the symptoms you may encounter if a configuration fails, and describes the advanced options you must use to debug your configuration.

Failure Symptoms Disable EPCS ID Check Disable AS Mode CONF_DONE Error Check PLC Settings Post-Chain Bitstream Pad Bytes Post-Device Bitstream Pad Bytes Bitslice Padding Value
Configuration failure occurs after a configuration cycle. — Yes Yes

Yes

3 		Yes 4 —
Decompression feature is enabled. — Yes Yes Yes 3 Yes 4 —
Encryption feature is enabled. — Yes Yes Yes 3 Yes 4 —
CONF_DONE stays low after a configuration cycle. — Yes Yes 5 Yes 3 Yes 4 —
CONF_DONE goes high momentarily after a configuration cycle. — Yes Yes 6 — — —
FPGA does not enter user mode even though CONF_DONE goes high. — — — Yes 3 Yes 4 —
Configuration failure occurs at the beginning of a configuration cycle. Yes — — — — —
Newly introduced EPCS, such as EPCS128. Yes — — — — —
Failure in .pof generation for EPC device using Intel® Quartus® Prime Convert Programming File Utility when the decompression feature is enabled. — — — — — Yes
3 Use only for multi-device chain
4 Use only for single-device chain
5 Start with positive offset to the PLC settings
6 Start with negative offset to the PLC settings
Level Two Title