Intel® Quartus® Prime Standard Edition User Guide: Programmer

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ID 683528
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Programming Intel FPGA Devices A. Intel® Quartus® Prime Standard Edition User Guides
1. Programming Intel FPGA Devices x
1.1. Programming Flow 1.2. Intel® Quartus® Prime Programmer Window 1.3. Programming and Configuration Modes 1.4. Design Security Keys 1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files 1.6. Convert Programming Files Dialog Box 1.7. Flash Loaders 1.8. JTAG Debug Mode for Partial Reconfiguration 1.9. Scripting Support 1.10. Programming Intel® FPGA Devices Revision History
1.1. Programming Flow x
1.1.1. Stand-Alone Intel® Quartus® Prime Programmer 1.1.2. Optional Programming or Configuration Files 1.1.3. Secondary Programming Files
1.2. Intel® Quartus® Prime Programmer Window x
1.2.1. Editing the Details of an Unknown Device 1.2.2. Setting Up the Hardware 1.2.3. Setting the JTAG Hardware 1.2.4. Using the JTAG Chain Debugger Tool
1.2.3. Setting the JTAG Hardware x
1.2.3.1. Running JTAG Daemon with Linux
1.5. Verifying if Programming Files Correspond to a Compilation of the Same Source Files x
1.5.1. Obtaining Project Hash for Arria® V, Stratix® V, Cyclone® V and Intel® MAX® 10 Devices 1.5.2. Obtaining Project Hash for Intel® Arria® 10 Devices
1.6. Convert Programming Files Dialog Box x
1.6.1. Debugging Your Configuration 1.6.2. Converting Programming Files for Partial Reconfiguration
1.6.2. Converting Programming Files for Partial Reconfiguration x
1.6.2.1. Generating .pmsf using a .msf and a .sof 1.6.2.2. Generating a .rbf for Partial Reconfiguration from a .pmsf file 1.6.2.3. Enable Decompression During Partial Reconfiguration Option
1.8. JTAG Debug Mode for Partial Reconfiguration x
1.8.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1.9. Scripting Support x
1.9.1. The jtagconfig Debugging Tool 1.9.2. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File 1.9.3. Generating Raw Binary File for Partial Reconfiguration using a .pmsf
1. Programming Intel FPGA Devices
A. Intel® Quartus® Prime Standard Edition User Guides

1.8.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode

To configure the Partial Reconfiguration bitstream in JTAG debug mode, follow these steps:
  1. In the Intel® Quartus® Prime Programmer GUI, right click a highlighted base bitstream (in .sof) and then click Add PR Programming File to add the PR bitstream (.rbf).
    Figure 1. Adding PR Programming File
  2. After adding the PR bitstream, you can change or delete the Partial Reconfiguration programming file by clicking Change PR Programming File or Delete PR Programming File.
    Figure 2. Change PR Programming File or Delete PR Programming File
  3. Click Start to configure the PR bitstream. The Intel® Quartus® Prime Programmer generates an error message if the specified device does not contain the PR IP core in the design (you must instantiate the Partial Reconfiguration IP core in your design to use the JTAG debug mode).
    Figure 3. Starting PR Bitstream Configuration
  4. Configure the valid .rbf in JTAG debug mode with the Intel® Quartus® Prime Programmer.
    Figure 4. Configuring Valid .rbf
  5. The JTAG debug mode is also supported if the PR IP core is pre-programmed on the specified device.
    Figure 5. Partial Reconfiguration IP Core Successfully Pre-programmed
  6. The Intel® Quartus® Prime Programmer reports error when you try to configure the corrupted .rbf in JTAG debug mode.
    Figure 6. Configuring Corrupted .rbf
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