Intel Agilex® 7 FPGA and SoC FPGA I-Series
I-Series devices offer the highest-performance I/O interfaces to address bandwidth-intensive applications. Manufactured on Intel 10 nm SuperFin process technology, this series builds upon F-Series device features offering transceiver rates up to 116 Gbps, PCIe 5.0 support, and cache- and memory-coherent attach to processors with Compute Express Link (CXL)1.
Intel Agilex® 7 FPGA and SoC FPGA I-Series
Interconnect Innovations
116 Gbps
highest transceiver data rate1
The industry’s
1st
PCIe 5.0 x16 PCI-SIG listed, 32 GT/s FPGA2
4X
higher CXL bandwidth per port vs. other FPGA Compute Express Link (CXL) implementations3
116 Gbps
highest transceiver data rate1
The industry’s
1st
PCIe 5.0 x16 PCI-SIG listed, 32 GT/s FPGA2
4X
higher CXL bandwidth per port vs. other FPGA Compute Express Link (CXL) implementations3
Benefits
Support the Most Demanding Bandwidth Requirements
Support industry-leading data rates up to 116 Gbps for a wide range of applications while supporting demanding bandwidth requirements with configurable networking support, including hard media access control (MAC), physical coding sublayer (PCS), and forward error correction (FEC) for Ethernet rates up to 400GE.
High-performance and Scalable with Fast Data Transfer Rates
Optimize I/O functionality allowing multiple hosts to connect through PCI Express (PCIe) 5.0 x16 Interface for high-performance and scalability, with data transfer rates from 2.5 giga transfers per second (GT/s) to 32.0 GT/s.
High-Speed, Low-Latency Cache and Memory-Coherent Interface
The new Compute Express Link (CXL) protocol provides a high-speed, low-latency cache, and memory-coherent interface to CPUs and workload accelerators for optimal workload acceleration and connection to FPGA-based discrete accelerators.
Use Cases and Applications
I-Series Addresses 400G IPU and Networking Solutions Requirements
Learn how I-Series devices deliver peak capacity, power efficiency, and performance for cloud (CSPs) and communications service providers (CoSPs) to improve revenue from infrastructure investment, lower total cost of ownership (TCO), increase networking capacity, security, and compute efficiency.
Intel Agilex® 7 FPGAs Target IPUs, SmartNICs, and 5G Networks
From edge to cloud, security challenges in the form of cyberattacks and data breaches loom ever larger as attacks on high-speed networks multiply. With the growing threats of cyberattacks and data breaches, use cases for secure, encrypted communications are plentiful, ranging from Open vSwitch (OvS), 5G network, and network storage.
Key Features
Logic Elements (LEs)
Innovations allow over 4 million LEs in a single monolithic fabric.
Heterogeneous 3D SiP Transceivers
Transceivers on heterogeneous 3D system-in-package (SiP) tiles support bandwidth capacities ranging up to 32 Gbps NRZ, and up to 116 Gbps PAM4.
High-Performance Crypto Blocks
Hardened 200G (Half Duplex) crypto cores supporting AES-GCM encryption/decryption, MACsec IP to secure network traffic.
Quad-core Arm Cortex-A53 SoC
Integrated hardened quad-core Arm Cortex-A53 processor option.
Additional Resources
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Intellectual Property
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FPGA Design Software
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Where to Buy
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Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex. Results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy.
Intel estimates based on Agilex FPGA CXL hard + soft IP test results (CXL link at 5.0 x16) vs. Xilinx FPGA using 3rd party CXL soft IP (CXL link at 4.0 x8), both interop with pre-production 4th Gen Intel® Xeon® processors.