MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

8.2.2. Register Map for IP version 2.0.0

Table 31.  CVO and Video Timing Generator Register Map for IP version 2.0.0
Address Register Name Access Description
Clocked Video Output Parameterization Registers

0x400

 VIP_PID RO Read this register to retrieve clocked video output IP product ID.

0x404

 VERSION RO Read this register to retrieve the version information for the Clocked Video Output IP.

0x408

 VID_FIFO_DEPTH RO The depth of the video input CDC FIFO.

0x410

 BPS RO The bits per video sample.

0x41C

 PIXELS_IN_PARALLEL RO The number of pixels per clock transferred on the AXI4-S buses.

0x420

 NUMBER_OF_COLOR_PLANES RO The number of color planes per pixel.

0x428

 CPU_CLK_FREQ_HZ RO The frequency of the processor interface clock in Hz.

0x42C

 TIM_DIMENSIONS RO If set to 1, the processor interface diagnostics include the dimensions of the input timing reference. If set to 0, the dimensions of the timing reference are not available to the processor interface.

0x430

 VID_IS_ASYNC RO If set to 1, the video input is treated as asynchronous to the timing reference. If set to 0, the video input must use the AXI4-S full-raster video clock.

0x434

 VID_DIMENSIONS RO If set to 1, the processor interface diagnostics include the dimensions of the video input. If set to 0, the dimensions of the video input are not available to the processor interface.

0x438

 VID_DEBUG RO If set to 1, the processor interface diagnostics include the locked, size err, and stall counters for the video input. If set to 0, the counters are not available to the processor Interface.

0x44C

 HSIZE RO The number of bits used to build the horizontal counters and comparators inside the Video Timing Generator. This determines the maximum width of raster that can be generated.

0x450

 VSIZE RO The number of bits used to build the vertical counters and comparators inside the Video Timing Generator. This determines the maximum height of raster that can be generated.

0x454

 BUILD_HARD_FRAME_LOCK RO If set to true, the internal Video Timing Generator turns on the hard frame lock function. If set to false, the internal Video Timing Generator turns off the hard frame lock.

0x458

 BUILD_SOFT_FRAME_LOCK RO If set to true, the internal Video Timing Generator turns on the soft frame lock function. If set to false, the internal Video Timing Generator turns off the soft frame lock.
Clocked Video Output Core Registers

0x540

 REG_STATUS RO Returns the status of the merge process.

0x544

 REG_BLACK_0 RW The initial value of “black” for color plane 0.

0x548

 REG_BLACK_1 RW The initial value of “black” for color plane 1.

0x54C

 REG_BLACK_2 RW The initial value of “black” for color plane 2.

0x554

 REG_FALLBACK RW Defines the behavior of the merge block if the video input fails.

0x568

 REG_VID_DIMS RO The active height and width of the video input.

0x56C

 REG_VID_FREQ_DIMS RO The frequency of the video input clock in Hz.

0x570

 REG_VID_CLKS_DIMS RO The number of video input clocks per input frame.

0x580

 REG_VID_LOCKED_COUNT RO Diagnostic counter that increments once at the start of each locked video frame.

0x584

 REG_VID_SIZE_ERR_COUNT RO Diagnostic counter that increments every time a mismatch between the video input and timing input is detected.

0x588

 REG_VID_STALL_COUNT RO Diagnostic counter that increments every time the video input stalls and is dropped by the merge block.
Video Timing Generator Registers

0x640

 REG_STATUS RO Reserved.

0x644

 REG_COMMIT RW Update internal parameters with new video standard.

0x648

 REG_MODE RW Control mode of operation.

0x64c

 REG_RESET_POS RW Expected position of the start of the frame input signal relative to the raster.

0x650

 REG_TOTALS RW Total height and width of the raster.

0x654

 REG_HB_END RW First active pixel of a line.

0x658

 REG_V1B_POS RW Start and end of vertical blanking for field 1.

0x65c

 REG_V2B_POS RW Start and end of vertical blanking for field 2.

0x660

 REG_FIELD_STARTS RW First lines of field 1 and 2.

0x664

 REG_HS_POS RW The start and end of horizontal sync.

0x668

 REG_V1S_START RW The horizontal and vertical position of the start of the vertical sync for field 1.

0x66c

 REG_V1S_END RW The horizontal and vertical position of the end of the vertical sync for field 1.

0x670

 REG_V2S_START RW The horizontal and vertical position of the start of the vertical sync for field 2.

0x674

 REG_V2S_END RW The horizontal and vertical position of the end of the vertical sync for field 2.

0x678

 REG_JITTER_CONT RW Timing parameters for the hard and soft frame lock.

0x67c

 REG_BLACK_0 RW The initial value of “black” for color plane 0.

0x680

 REG_BLACK_1 RW The initial value of “black” for color plane 1.

0x684

 REG_BLACK_2 RW The initial value of “black” for color plane 2.

0x68c

 REG_FRAME_COUNTS RO Returns the total number of frames output and the number of external frame starts received.

0x690

 REG_FRAME_LENGTH RO The number of video clocks between consecutive frame start input signals.

0x694

 REG_VTOTAL_ADJ RO The total height of the raster after adjustment for soft lock.

0x698

 REG_VID_FREQ RO The frequency of the video clock in Hz.

0x69c

 REG_GENLOCK_STATS0 RO Diagnostics for hard and soft frame lock.

0x6a0

 REG_GENLOCK_STATS1 RO Diagnostics for soft frame lock.
Level Two Title