MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

3.3.1. Generated File Structure

The Quartus® Prime Pro Edition software generates the following IP core output file structure:

Figure 12. Directory Structure
Table 15.  Directory Structure and Files
Directory/File Description
<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
<my_ip>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<my_ip>.qgsimc Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP. This comparison determines if Platform Designer can skip regeneration of the HDL.
<my_ip>.qgsynth Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP. This comparison determines if Platform Designer can skip regeneration of the HDL.
<my_ip>.qip Contains all the required information about the IP component to integrate and compile the IP component in the Quartus® Prime software.
<my_ip>.csv Contains information about the upgrade status of the IP component.
<my_ip>.bsf A Block Symbol File (.bsf) representation of the IP variation for use in Block Diagram Files (.bdf).
<my_ip>.spd Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with the information about the memories that you can initialize.
<my_ip>_bb.v Use the Verilog black box (_bb.v) file as an empty module declaration for use as a black box.
<my_ip>_inst.v or <my_ip>_inst.vhd HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<my_ip>.v or <my_ip>.vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation.
sim/mentor/ Contains a Questa* – Altera® FPGA Edition script msim_setup.tcl to set up and run a simulation.
sim/synopsys/vcsmx/ Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS* MX simulation.
sim/xcelium/ Contains a shell script xcelium_setup.sh and other setup files to set up and run a Xcelium* simulation.
sim/common/ Contains a set of Tcl files, <simulator>_files.tcl, which provide all design related simulation information required by a corresponding simulation script. The Tcl file contains designs from current system-level hierarchy, and references to sub-systems and IP components.
<IP_submodule>/ For each generated IP submodule directory, Platform Designer generates /synth and /sim sub-directories under IP-specific directories.
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