MIPI DSI-2 IP User Guide

Download PDF
ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

3.4.1. Generated Directory Structure and Files

Table 16.  Generated Files in the quartus Directory and File DescriptionsThe quartus directory contains the Quartus Prime project files, including compilation reports:
File Description
dsi2_<variant>_sys.qpf Quartus® Prime project file.
dsi2_<variant>_sys.qsf Quartus® Prime .qsf assignment file.
Table 17.  Generated Files in the rtl Directory and File Descriptions for Synthesis and Full SimulationsThe rtl directory contains all synthesizable components, including the system interconnect and Platform Designer generated IP:
Directory or File Description
dsi2_dphy_sys.qsys Platform Designer file that contains MIPI DSI-2 and DPHY system definition.
dsi2_dphy_sys/ Directory that contains Platform Designer generated files.
ip/dsi2_dphy_sys Directory that contains the Platform Designer generated IP files.

.../dsi2_dphy_sys_dsi2_tx.ip

.../dsi2_dphy_sys_dsi2_tx/

 IP definition file for MIPI DSI-2.

.../dsi2_dphy_sys_mipi_dphy.ip

.../dsi2_dphy_sys_mipi_dphy/

 IP definition file for MIPI D-PHY IP (unused in the fast simulation variant).

.../dsi2_dphy_sys_reset_release_0.ip

.../dsi2_dphy_sys_reset_release_0/

 IP definition file for Reset Release.

.../dsi2_dphy_sys_dsi2_tx_axi4s_clk_bridge.ip

.../dsi2_sys_dphy_dsi2_tx_axi4s_clk_bridge/

 IP definition file for Clock Bridge for MIPI DSI-2 AXI-S Clock.

.../dsi2_dphy_sys_dsi2_tx_axi4s_reset_bridge.ip

.../dsi2_dphy_sys_dsi2_tx_axi4s_reset_bridge/

 IP definition file for Reset Bridge for MIPI DSI-2 AXI-S Clock.

.../dsi2_dphy_sys_mipi_dphy_link1_link_core_clock_bridge.ip

.../dsi2_dphy_sys_mipi_dphy_link1_link_core_clock_bridge/

 IP definition file for Clock Bridge for DPHY Clock.

.../dsi2_dphy_sys_mipi_dphy_link1_link_core_reset_bridge.ip

.../dsi2_dphy_sys_mipi_dphy_link1_link_core_reset_bridge.ip

 IP definition file for Reset Bridge for DPHY Clock.
Table 18.  Generated Files in ed_sim Directory and File DescriptionsThe ed_sim directory contains all simulation files and scripts:
Directory / File Description
dsi2_ed_sim_tb.sv Top-level testbench file.
dut_wrapper.sv Wrapper around MIPI CSI-2 TX, RX BFM and MIPI Loopback.

In the fast simulation variant, the PPI interface from the MIPI DSI-2 TX IP is looped back into the MIPI DSI-2 RX BFM.

In the full simulation variant, the MIPI DSI-2 TX PPI is connected to MIPI D-PHY TX IP, then looped back to MIPI D-PHY RX IP and into the MIPI DSI-2 RX BFM.
cfg_pkg.sv SystemVerilog package containing generated IP parameters.
sim.spd File used by Quartus® Prime ip-make-simscript.
mipi_*.sv Simulation-only encrypted MIPI DSI-2 receiver bus functional model.
hdl/ Contains Encrypted Verification IP files.
sim/aldec/ Contains Riviera-PRO* simulator script.
run_rivierapro_setup.tcl Script that runs Riviera-PRO simulation.
rivierapro_setup.tcl Setup file for Riviera-PRO simulation.
sim/mentor/ Contains Mentor simulator script.
run_msim_setup.tcl Script that runs QuestaSIM* simulation.
msim_setup.tcl Setup file for QuestaSIM* simulation.
sim/synopsys/vcsmx/ Contains Synopsys VCS* MX simulator script.
sim.sh Script that runs VCS* MX simulation.
vcsmx_setup.sh Setup script for VCS* MX simulation.
synopsys_sim_setup.sh Setup file for VCS* MX simulation.
sim/xcelium/ Contains Xcelium* simulator script.
xcelium_setup.sh Script that runs Xcelium* simulation.
Level Two Title