MIPI DSI-2 IP User Guide

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ID 869461
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the MIPI DSI-2 IP With Your Application 5. Synthesizing the IP 6. Simulating the IP 7. Appendix A: Functional Description 8. Appendix B: Registers 9. Document Revision History for the MIPI DSI-2 IP User Guide
1. Overview x
1.1. About the MIPI DSI-2 IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow
1.1. About the MIPI DSI-2 IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.5. IP Design Flow x
1.5.1. System Level Block Diagram
2. Quick Start Guide x
2.1. Synthesizing the Design Example 2.2. Simulating the Design Example
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Configuring the MIPI DSI-2 IP 3.3. Generating HDL for Synthesis and Simulation 3.4. Generating the Design Example 3.5. Compiling the Design Example
3.2. Configuring the MIPI DSI-2 IP x
3.2.1. Configuring the MIPI DSI-2 IP Parameters
3.2.1. Configuring the MIPI DSI-2 IP Parameters x
3.2.1.1. IP Tab Options 3.2.1.2. Video Timing Tab Options 3.2.1.3. Design Example Tab Options
3.2.1.2. Video Timing Tab Options x
3.2.1.2.1. Configuration Requirements 3.2.1.2.2. Timing Calculation Examples
3.3. Generating HDL for Synthesis and Simulation x
3.3.1. Generated File Structure
3.4. Generating the Design Example x
3.4.1. Generated Directory Structure and Files
4. Integrating the MIPI DSI-2 IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Connecting the Video Input Interface 4.6. Connecting the MIPI PHY-Protocol Interface 4.7. Connecting the Control Interface
4.1. High-Level Interface Types x
4.1.1. Transmitter Input Video Interface Signals 4.1.2. Transmitter PHY-Protocol Interface (PPI) Signals 4.1.3. Avalon Memory-Mapped Interface Control Signals 4.1.4. Additional Control Signals
4.3. Implementing Required Clocking x
4.3.1. MIPI PPI Clocks 4.3.2. Video Input Clock 4.3.3. Control Interface Clock
6. Simulating the IP x
6.1. Design Example Simulation Features 6.2. Design Example Components 6.3. Supported Simulation EDA Tools 6.4. Simulating the Design Example
8. Appendix B: Registers x
8.1. MIPI DSI-2 IP Base Registers 8.2. CVO and Video Timing Generator Registers
8.2. CVO and Video Timing Generator Registers x
8.2.1. Register Map for IP version 1.0.0 8.2.2. Register Map for IP version 2.0.0
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the MIPI DSI-2 IP With Your Application
5. Synthesizing the IP
6. Simulating the IP
7. Appendix A: Functional Description
8. Appendix B: Registers
9. Document Revision History for the MIPI DSI-2 IP User Guide

4.5. Connecting the Video Input Interface

The video input interface to the MIPI DSI-2 IP uses the Altera Streaming Video Protocol (full variant). This is based on the AMBA AXI4-Stream interface, carrying video and control packets describing the video structure.
The interface is synchronous to the clk clock. Flow control is implemented using the TVALID and TREADY signals.
Table 26.  Video Interface Signals
Signal Name Width Direction Description
axi4s_vid_in_tdata TDATA_WIDTH Input This carries the pixel and control packet data. The width follows the interface configuration as described in the Protocol specification and also displayed on the IP parameter editor.
axi4s_vid_in_tvalid 1 Input Indicates that the current cycle carries valid data.
axi4s_vid_in_tready 1 Output Asserted by the IP when the current cycle can be processed. If this signal is deasserted, the contents of the interface are not captured on this cycle.
axi4s_vid_in_tlast 1 Input Indicates the last cycle in a control or video packet.
axi4s_vid_in_tuser TDATA_WIDTH/8 Input
  • Bit [0] is asserted for the first cycle in a video frame.
  • Bit [1] is asserted for the first cycle in a control (Image Information) packet.

For more details on the Altera Streaming Video protocol and pixel formatting, refer to Altera FPGA Streaming Video Protocol Specification.

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