AN 1014: Implementing Analog-to-Digital Converter Multilink Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

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ID 857717
Date 11/24/2025
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Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP x
1.1. ADC to Agilex™ 7 Dual Link Design Overview 1.2. ADC to Agilex™ 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Agilex™ 7 Dual Link 1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing 1.5. Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1.3. Synchronized ADC to Agilex™ 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.3. Editing Simulation Testbench for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.4. Adding IP Signals to the Simulation Waveform 1.3.1.5. Updating the Simulation Script 1.3.1.6. Simulating the Dual Link Design 1.3.1.7. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing x
1.4.1. Downloading and Operating the Design Example
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

1.3.1.7. Viewing the Simulation Results

The simulation testbench prints the results at the transcript or terminal where you execute the simulation script. The following example shows the printout and waveform of the simulation in the ModelSim‐ Altera® Pro FPGA Edition:

If the simulation passes, the transcript section prints TESTBENCH_PASSED: SIM PASSED! as shown in the following figure.

Figure 12. ModelSim‐ Altera® Pro FPGA Edition Simulation Results Transcript

If the simulation fails, the transcript section prints TESTBENCH_FAILED: SIM FAILED! along with the failure reason.

If you want to view the waveform, the following events occur during link initialization.

  1. After the /tb_top/ninit_done and global reset are deasserted.
  2. The user logic asserts the F-Tile JESD204C IP and configuration reset to the F-Tile JESD204C IP TX, j204c_tx_avs_rst_n = 0, j204c_tx_rst_n = 0, and reconfig_xcvr_reset = 1.
    Note: If you assert j204c_tx_avs_rst_n and reconfig_xcvr_reset, j204c_tx_rst_n is required to be asserted as well. You can opt to assert j204c_tx_rst_n without asserting j204c_tx_avs_rst_n and reconfig_xcvr_reset.
  3. The user logic deassert j204c_tx_avs_rst_n and reconfig_xcvr_reset and perform configurations of the PHY and IP. At the same, wait for IOPLL to lock.
  4. After all relevant PHY channels are fully in reset, the IP core asserts j204c_tx_rst_ack_n to the user logic. Knowing the relevant channels are in proper reset states, the user logic can release the reset to the IP core when possible (j204c_tx_rst_n = 1). Use j204c_tx_rst_ack_n as an indicator to deassert j204c_tx_rst_n = 1.
  5. The user logic deasserts the IP reset (j204c_tx_rst_n = 1).
  6. The IP asserts j204c_tx_avst_ready = 1. The F-Tile JESD204C TX IP core is operational.
  7. The jesd204c_tx_avst_data for both IP only start sending data after both j204c_tx_avst_ready has asserted. This is to ensure synchronization.
    Figure 13. ModelSim‐ Altera® Pro FPGA Edition Simulation Waveform for F-Tile JESD204C TX IP
  8. The RX transport layer is out of reset when the /tb_top/rx_rst_n is deasserted. The RX transport layer asserts the j204c_rx_avst_ready signal to the JESD204C FPGA IP.
  9. The RX JESD204C IPs achieve sync header alignment (j204c_rx_sh_lock is asserted) when 64 consecutive valid sync headers are detected.
  10. The RX JESD204C IPs achieve extended multiblock alignment (j204c_rx_emb_lock is asserted) when 4 consecutive valid sequences are detected. A valid sequence is defined as correct EoEMB and EoMB values for a full E*32-bit sync transition stream.
  11. j204c_rx_alldev_lane_align is asserted when both RX JESD204C IPs achieve lane alignment.
  12. j204c_rx_avst_valid is asserted when the RX transport layer streams user data to the application layer together with the start-of-multiblock (j204c_rx_somb) and start-of-extended-multiblock (j204c_rx_soemb) markers.
  13. The command channel of the RX JESD204C IP outputs the CRC-12 signal in the sync header stream. No CRC error (j204c_rx_crc_err) is detected. No parity error (j204c_rx_cmd_par_err) is detected at the command channel.
    Figure 14. ModelSim‐ Altera® Pro FPGA Edition Simulation Waveform for F-Tile JESD204C RX IP
  14. The pattern checker checks the received sample data from the RX transport layer. No error (/tb_top/data_error) is detected.
  15. The pattern checker checks the received sync header from the RX JESD204C IP. No error (/tb_top/cmd_data_error) is detected.
  16. No TX and RX link errors or interrupts (/tb_top/tx_link_error and /tb_top/rx_link_error) are being asserted by both TX and RX JESD204C IPs. The testbench asserts the test_passed flag.
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