AN 1014: Implementing Analog-to-Digital Converter Multilink Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

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ID 857717
Date 11/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP x
1.1. ADC to Agilex™ 7 Dual Link Design Overview 1.2. ADC to Agilex™ 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Agilex™ 7 Dual Link 1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing 1.5. Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1.3. Synchronized ADC to Agilex™ 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.3. Editing Simulation Testbench for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.4. Adding IP Signals to the Simulation Waveform 1.3.1.5. Updating the Simulation Script 1.3.1.6. Simulating the Dual Link Design 1.3.1.7. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing x
1.4.1. Downloading and Operating the Design Example
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

1.4.1. Downloading and Operating the Design Example

The design example contains an F-Tile JESD204C FPGA IP designs for RX-multilink as well as TX-RX multilink design for hardware testing. This design example is verified using simulation and hardware testing.

Follow these steps to download and operate the design example:
  1. Download the design example file (.par) from Design Store and restore the design using Quartus® Prime Pro Edition software version 23.2 and above.
  2. In the Quartus® Prime Pro Edition software, click File > Open Project to extract the .par design example.
  3. Extract the files and folders from the simulation.zip file into simulation folder.
  4. Follow the instructions in Simulating the Dual Link Design. The explanations of the simulation results are presented in Viewing the Simulation Results.
Related Information
Level Two Title