1.3.2. Design Synthesis Guidelines

AN 1014: Implementing Analog-to-Digital Converter Multilink Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

Download PDF

ID 857717

Date 11/24/2025

Version current

Public

Document Table of Contents

Document Table of Contents x

1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP x

1.1. ADC to Agilex™ 7 Dual Link Design Overview 1.2. ADC to Agilex™ 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Agilex™ 7 Dual Link 1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing 1.5. Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

1.3. Synchronized ADC to Agilex™ 7 Dual Link x

1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines

1.3.1. Design Simulation Guidelines x

1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.3. Editing Simulation Testbench for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.4. Adding IP Signals to the Simulation Waveform 1.3.1.5. Updating the Simulation Script 1.3.1.6. Simulating the Dual Link Design 1.3.1.7. Viewing the Simulation Results

1.3.2. Design Synthesis Guidelines x

1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software

1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing x

1.4.1. Downloading and Operating the Design Example

1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

1.1. ADC to Agilex™ 7 Dual Link Design Overview

1.2. ADC to Agilex™ 7 Dual Link Design Implementation Guidelines

1.3. Synchronized ADC to Agilex™ 7 Dual Link

1.3.1. Design Simulation Guidelines

1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link

1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link

1.3.1.3. Editing Simulation Testbench for Synchronized ADC to Agilex™ 7 Dual Link

1.3.1.4. Adding IP Signals to the Simulation Waveform

1.3.1.5. Updating the Simulation Script

1.3.1.6. Simulating the Dual Link Design

1.3.1.7. Viewing the Simulation Results

1.3.2. Design Synthesis Guidelines

1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link

1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link

1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link

1.3.2.4. Compiling the Design in Quartus® Prime Software

1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing

1.4.1. Downloading and Operating the Design Example

1.5. Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP