AN 1014: Implementing Analog-to-Digital Converter Multilink Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
ID
857717
Date
11/24/2025
Public
1.1. ADC to Agilex™ 7 Dual Link Design Overview
1.2. ADC to Agilex™ 7 Dual Link Design Implementation Guidelines
1.3. Synchronized ADC to Agilex™ 7 Dual Link
1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing
1.5. Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link
1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link
1.3.1.3. Editing Simulation Testbench for Synchronized ADC to Agilex™ 7 Dual Link
1.3.1.4. Adding IP Signals to the Simulation Waveform
1.3.1.5. Updating the Simulation Script
1.3.1.6. Simulating the Dual Link Design
1.3.1.7. Viewing the Simulation Results
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link
1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link
1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link
1.3.2.4. Compiling the Design in Quartus® Prime Software
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
This application note provides guidelines on how to scale up the single link of the F-Tile JESD204C IP design example generated from the Quartus® Prime software to handle a dual link system. A single link in JESD204C has one or more high speed transceiver lanes or channels.
In some JESD204C applications, multiple analog-to-digital converters (ADCs) are used to sample the analog signals synchronously. Hence, synchronization between multiple converters in the array is required. In these applications, multiple converters interface with a single logic device, such as the Agilex™ 7 FPGA F-tile.
Before implementing the dual link design, you must generate the receiver (RX) single-link design example from the Quartus® Prime software. Altera® recommends that you perform an RTL simulation on this single link design example to confirm the functionality matches your expectation before transforming the design example to the dual link design. The guidelines in the following section assume the JESD204C parameters for each link in the dual link design are identical.
Figure 1. High Level Overview of F-Tile JESD204C Dual LinkFigure shows one dual link. All lanes are aligned.
Section Content
ADC to Agilex 7 Dual Link Design Overview
ADC to Agilex 7 Dual Link Design Implementation Guidelines
Synchronized ADC to Agilex 7 Dual Link
Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing
Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex 7 FPGA F-Tile JESD204C RX IP