AN 1014: Implementing Analog-to-Digital Converter Multilink Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

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ID 857717
Date 11/24/2025
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Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP x
1.1. ADC to Agilex™ 7 Dual Link Design Overview 1.2. ADC to Agilex™ 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Agilex™ 7 Dual Link 1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing 1.5. Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1.3. Synchronized ADC to Agilex™ 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.3. Editing Simulation Testbench for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.4. Adding IP Signals to the Simulation Waveform 1.3.1.5. Updating the Simulation Script 1.3.1.6. Simulating the Dual Link Design 1.3.1.7. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing x
1.4.1. Downloading and Operating the Design Example
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

1.3. Synchronized ADC to Agilex™ 7 Dual Link

To synchronize multiple RX IPs within the Agilex™ 7 device, connect the following signals from each IP with an AND gate respectively:
  • j204c_rx_dev_lane_align
  • j204c_rx_dev_emblock_align

The output of the AND gate connects to the j204c_rx_alldev_lane_align and j204c_rx_alldev_emblock_align ports of each IP. Refer to Figure 4 for the required connections. The IPs need to be out of reset simultaneously to complete the link initialization sequence. Multiple IPs are put into the same JESD204C subsystem so that the reset of each IP is released by the same reset sequencer simultaneously.

Table 1.  IP Ports Connection Summary Table summarizes the IP ports connection for each subclass in the dual link for multi-device synchronization.
Subclass j204c_rx_alldev_lane_align j204c_rx_alldev_emblock_align Reset Remark
0 ANDed and re-distribute ANDed and re-distribute Simultaneous Refer to Figure 4
1

For subclass 1, the SYSREF pulse is the timing reference of the entire JESD204C subsystem. It is important to phase-align the SYSREF pulses to the FPGA and converters.

Note: For Subclass 0 IPs, connect the j204c_rx_sysref port to ground.
Figure 4. Design Simulation and Synthesis Implementation Guidelines
Figure 5. Clock and Reset Scheme of the Synchronized Dual Link
Note: To add F-Tile JESD204C IPs for interfacing with more than one ADC, modifications are needed to the Platform Designer system and top-level HDL of the design example.

Section Content
Design Simulation Guidelines
Design Synthesis Guidelines

Level Two Title