AN 1014: Implementing Analog-to-Digital Converter Multilink Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

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ID 857717
Date 11/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP x
1.1. ADC to Agilex™ 7 Dual Link Design Overview 1.2. ADC to Agilex™ 7 Dual Link Design Implementation Guidelines 1.3. Synchronized ADC to Agilex™ 7 Dual Link 1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing 1.5. Document Revision History for AN 1014: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP
1.3. Synchronized ADC to Agilex™ 7 Dual Link x
1.3.1. Design Simulation Guidelines 1.3.2. Design Synthesis Guidelines
1.3.1. Design Simulation Guidelines x
1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.3. Editing Simulation Testbench for Synchronized ADC to Agilex™ 7 Dual Link 1.3.1.4. Adding IP Signals to the Simulation Waveform 1.3.1.5. Updating the Simulation Script 1.3.1.6. Simulating the Dual Link Design 1.3.1.7. Viewing the Simulation Results
1.3.2. Design Synthesis Guidelines x
1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link 1.3.2.4. Compiling the Design in Quartus® Prime Software
1.4. Instantiating TX simplex into RX Multi-Link Design for Loopback Hardware Testing x
1.4.1. Downloading and Operating the Design Example
1. Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP

1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Agilex™ 7 Dual Link

Several modifications to the top-level SDC constraint, jesd204c_f_ed_rx.sdc, are needed to ensure that the newly added IPs are fully constrained:

In the set_clock_groups constraints, add entries for the newly added IPs. 
set_clock_groups -asynchronous -group {mgmt_clk} \
-group {u_j204c_f_rx_ss|core_pll|core_pll_clk_1x u_j204c_f_rx _ss|core_pll|core_pll_refclk} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_clkout|ch0} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_clkout|ch1} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_clkout|ch2} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_clkout|ch3} \
-group {altera_reserved_tck}

set_clock_groups -async -group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_transfer_clk|ch0} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_transfer_clk|ch1} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_transfer_clk|ch2} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|<ip core instance name>|intel_jesd204c_f|rx_transfer_clk|ch3} \
-group {u_j204c_f_rx_ss|core_pll|core_pll_clk_1x } \
-group {mgmt_clk}
Note: To identify the appropriate channels, click Compilation Report > Timing Analyzer > Clocks > Report Clocks.

<ip core instance name> is the name for the duplicated copy of the JESD204C IP that you named in step 4.

The following example has the newly added design entities: 
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|intel_jesd204c_f_1|intel_jesd204c_f| |rx_clkout|ch0} \
-group {u_j204c_f_rx_ss|j204c_f_rx_ip|intel_jesd204c_f_1|intel_jesd204c_f| rx_transfer_clk|ch0} \
Level Two Title