GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
ID
848344
Date
4/07/2025
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Configuration Register
3.11. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.12. Configurable Quartus® Prime Software Settings
3.13. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. TX Datapath Options
3.3.4. RX Datapath Options
3.3.5. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.6. FEC Options
3.3.7. PCS Options
3.3.8. Avalon® Memory-Mapped Interface Options
3.3.9. Register Map IP-XACT Support
3.3.10. Analog Parameter Options
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. RX PMA Status Signals
3.4.7. TX and RX PMA and Core Interface FIFO Signals
3.4.8. Avalon Memory-Mapped Interface Signals
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Run-time Reset Sequence—TX
3.8.5. Run-time Reset Sequence—RX
3.8.6. Run-time Reset Sequence—TX + RX
3.8.7. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.8.8. TX PLL Lock Loss
3.8.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
5.1. IP Requirements
5.2. IP Parameters
5.3. IP Port List
5.4. GTS Reset Sequencer Intel FPGA IP General Interface
5.5. GTS Reset Sequencer Intel FPGA IP Design Flow
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
3.3.7. PCS Options
The GTS PMA/FEC Direct PHY Intel FPGA IP supports various PCS direct modes. To enable the PCS direct mode, you must first set the PMA configuration rules parameter as Basic in the Common Datapath Options tab. You can then enable this functionality in the parameter editor by selecting the Enable Custom PCS option in the PCS Options tab. If Enable Custom PCS is off, then the other options are grayed out in the GUI.
The GTS PMA/FEC Direct PHY Intel FPGA IP supports the following custom PCS modes:
- IEEE MII Interface (supports MII coder and scrambler)
- IEEE_FLEXE_66 (supports scrambler)
- PCS66
Figure 35. PCS Options in Parameter Editor
Parameter | Values | Description |
---|---|---|
Enable Custom PCS | On/Off | Enables or disables the custom PCS direct mode. Default value is Off. |
Select Custom PCS interface |
|
Selects the PCS direct mode from various options. Default value is IEEE MII Interface. |