2.5. Simulating the Design Example Testbench
The design example testbench simulates your generated design.
To simulate the design, perform the following steps:
- Change the working directory to <example_design_directory>/ed_sim/<Simulator>.
- In the command line, run the simulation script. The table below shows the commands to run the supported simulators.
Simulator Command QuestaSim* / ModelSim* vsim -do run_tb_top.tcl VCS* MX sh run_tb_top.sh Riviera-PRO* vsim -do run_tb_top.tcl Xcelium* sh run_tb_top.sh The simulation ends with messages that indicate whether the run was successful or not.