GTS JESD204B Intel® FPGA IP Design Example User Guide

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ID 844839
Date 6/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide 2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204B Design Example 4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.5. Simulating the Design Example Testbench x
2.5.1. Simulation Testbench
3. Detailed Description for the GTS JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. GTS JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204B Design Example
4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide

2.4. Dual Simplex Design Example

Figure 4. Dual Simplex Design Example Block Diagram

The Dual Simplex example design currently supports Duplex Case only with TX and RX in the same or mixed configuration, e.g. data rate, number of lanes (L), number of converters per device (M), number of octets per frame (F), etc. For more information, refer to the Dual Simplex Support section in the GTS JESD204B Intel® FPGA IP User Guide.

To generate the design example:

  1. Create a project targeting Agilex™ 5 or Agilex™ 3 device family and select the desired device.
  2. In the IP Catalog, Tools > IP Catalog, select GTS JESD204B Intel® FPGA IP . Modify the IP Tab for required JESD configurations. The JESD IP supports same or mixed configuration for both TX and RX. Set the data path as Duplex mode.
  3. In the GTS JESD204B Intel® FPGA IP GUI, go to the Example Design tab and enable Enable dual simplex generation.
  4. Generate the example design and after opening the example design, choose the Dual Simplex assignment editor in the Assignments menu.
  5. Verify the TX and RX PHY relative offsets. Save assignments and run IP generation in Quartus® Prime. This will generate the HSSI dual simplex generation.
  6. Run the full compilation and perform the hardware test according to Hardware Test for System Console Control Design Example.
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