GTS JESD204B Intel® FPGA IP Design Example User Guide

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ID 844839
Date 6/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide 2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204B Design Example 4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.5. Simulating the Design Example Testbench x
2.5.1. Simulation Testbench
3. Detailed Description for the GTS JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. GTS JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204B Design Example
4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide

3.6.1. Board Connectivity

If you are performing hardware testing on the selected development kits, generate the design example with the appropriate target development kit selected.
Note: Running the hardware test with the design generated as-is is only possible when the GTS JESD204B Intel® FPGA IP is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 20.   Agilex™ 5 FPGA E-Series 065B Premium Development Kit (A5ED065BB32AE6SR0) Board ConnectivityThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for all supported target development kits.
Port Name Port Description Board Component Component Description
global_rst_n Global reset U5G Refer to the MAX® 10 FPGA Device Datasheet
refclk_xcvr Transceiver reference clock input U412 Si5332 Clock Generator (OUT0)
refclk_core Core PLL reference clock input U412 Si5332 Clock Generator (OUT2)
mgmt_clk Control clock U411 Si5332 Clock Generator (OUT4)

tx_serial_data[0-3]

tx_serial_data[4-7]

TX serial data

J12

J13

QSFP1 Connector (GTS Bank 1A)

QSFP2 Connector (GTS Bank 1B)

rx_serial_data[0-3]

rx_serial_data[4-7]

RX serial data

J12

J13

QSFP1 Connector (GTS Bank 1A)

QSFP2 Connector (GTS Bank 1B)
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