3.2.2. Parallel I/O Core
The Parallel I/O (PIO) modules provide general input/output (I/O) access from the Avalon® master (JTAG to Avalon® master bridge). There are two sets of 32-bit PIO registers:
- Status registers—input from the HDL components to the Avalon® master
- Control registers—output from the Avalon® master to the HDL components
The registers are assigned in the top level HDL file (io_status for status registers, io_control for control registers). The tables below describe the signal connectivity for the status and control registers.
Bit | Signal |
---|---|
0 | Core PLL locked |
1 | TX reset handshake acknowledge status (j204b_tx_rst_ack_n) |
2 | RX reset handshake acknowledge status (j204b_rx_rst_ack_n) |
3 | Test pattern checker data error (for duplex and simplex RX data path only – avst_patchk_data_error) |
4 | TX link error (for duplex and simplex TX data path only – tx_link_error) |
5 | RX link error (for duplex and simplex RX data path only – rx_link_error) |
31:6 | Reserved |
Bit | Signal |
---|---|
29:0 | Reserved |
30 | Global reset |
31 | SYSREF |