GTS JESD204B Intel® FPGA IP Design Example User Guide

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ID 844839
Date 6/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide 2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204B Design Example 4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.5. Simulating the Design Example Testbench x
2.5.1. Simulation Testbench
3. Detailed Description for the GTS JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. GTS JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204B Design Example
4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide

2.2. Hardware and Software Requirements

Altera uses the following software to test the design examples in a Linux system:

  • Quartus® Prime Pro Edition software
  • ModelSim* , QuestaSim* , Riviera-PRO* , Xcelium* , or VCS* MX simulator
  • Agilex™ 5 FPGA E-Series 065B Premium Development Kit (A5ED065BB32AE6SR0) for hardware testing
Level Two Title