GTS JESD204B Intel® FPGA IP Design Example User Guide

ID 844839
Date 6/06/2025
Public
Document Table of Contents

3.2.1. JESD204B Subsystem in Platform Designer

The JESD204B subsystem instantiates the following modules:

  • GTS JESD204B Intel® FPGA IP
  • GTS Reset Sequencer Intel® FPGA IP
  • Reset sequencers
  • Avalon® memory-mapped bridge

GTS JESD204B IP

The generated design example is a self-contained system with its own JESD204B IP core instantiation that is separate from the IP core that is generated from the IP tab. The JESD204B IP base core and PHY layer connect to System Console through the Avalon® memory-mapped interconnect. The JESD204B IP core uses three separate Avalon® memory-mapped ports:

  • Base core TX data path—for accessing the TX CSR
  • Base core RX data path—for accessing the RX CSR
  • PHY layer—for accessing the transceiver PHY CSR

The structure of the design example varies depending on the values of these JESD204B IP core parameters:

  • Data path:
    • Duplex—both TX and RX data paths and CSR interfaces present
    • Transmitter—only TX data path and CSR interface present
    • Receiver—only RX data path and CSR interface present

GTS Reset Sequencer Intel® FPGA IP

In an Agilex™ 5 or Agilex™ 3 device, there is a new requirement to instantiate the GTS Reset Sequencer Intel® FPGA IP for proper transceiver reset operation. This IP can be found in the IP catalog and is required to be instantiated only once for each side of the device. Ensure to select the number of Lane parameter according to the total number of channels used for the particular side of the device this reset sequencer IP is instantiated for.
Note: For more information on connecting the GTS Reset Sequencer Intel® FPGA IP, refer to the Implementing the GTS Reset Sequencer Intel® FPGA IP section in the GTS Transceiver PHY User Guide.

Reset Sequencers

The reset sequencer is a standard Platform Designer component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:

  1. Core PLL reset—resets the core PLL
  2. TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs
  3. TX/RX JESD204B IP MAC and PHY reset—resets the TX/RX JESD204B IP core base module and the PHY
  4. TX/RX link reset—resets the TX/RX transport layer link interface
  5. TX/RX frame reset—resets the TX/RX transport layer, upstream and downstream modules

The reset sequencer has hard and soft reset options. The hard reset port connects to the global reset input pin in the top level design. The soft reset is activated via Parallel I/O's Avalon® memory-mapped interface by TCL scripts (System Console control). When you assert a hard or soft reset, the reset sequencer cycles through all the various module resets based on a pre-set sequence..

Two reset sequencers are used for independent TX and RX resets. The following tables show the reset sequencer input output port connections.

Table 10.  Reset Sequencer 0 Output Port Usage
Reset Sequencer Input/Output Reset Signal
reset_in0 mgmt_rst_in_n
reset_out0 core_pll_rst
reset_out1 j204b_tx_avs_rst_n
reset_out2 j204b_tx_rst_n
reset_out3 txlink_rst_n (transport layer)
reset_out4 txframe_rst_n (transport layer)
Table 11.  Reset Sequencer 1 Output Port Usage
Reset Sequencer Input/Output Reset Signal
reset_in0 mgmt_rst_in_n
reset_out0 j204b_rx_avs_rst_n
reset_out1 j204b_rx_rst_n
reset_out2 rxlink_rst_n (transport layer)
reset_out3 rxframe_rst_n (transport layer)
Figure 8. Reset Sequence
  1. Reset Release Intel FPGA IP asserts the nINIT_DONE when the FPGA enters user mode.
  2. The deasserted global_rst_n releases the example design reset. The mgmt_rst_in_n deasserts the reset input of reset sequencers.
  3. The core PLL (IOPLL) resets are released.
  4. When the core PLL is locked, the JESD204B IP CSR resets (j204b_tx/rx_avs_rst_n) are released and start CSR configuration.
  5. For the transmitter, when the CSR configuration is done, the core PLL is locked and the IP reset handshake indicates j204b_tx_rst_ack_n = 0, release JESD204B TX reset, j204b_tx_rst_n = 1.
  6. The j204b_tx_rst_ack_n deasserts to 1 when the TX PHY is out of reset.
  7. Finally, the JESD204B IP asserts j204b_tx_out_of_reset = 1. The design example's txlink_rst_n and txframe_rst_n are released. The transport layer assembler and pattern generator are now active. The IP core will assert both j204b_tx_frame_ready =1 and j204b_tx_link_ready =1 signals. The Avalon® streaming interface data transfer begins when JESD204B IP is ready.
  8. For the receiver, when CSR configuration is done, the core PLL is locked and the IP reset handshake indicates j204b_rx_rst_ack_n = 0, release JESD204B RX reset, j204b_rx_rst_n.
  9. The j204b_rx_rst_ack_n deasserts to 1 when the RX PHY is out of reset.
  10. Finally, the JESD204B IP asserts j204b_rx_out_of_reset = 1. The design example's rxlink_rst_n and rxframe_rst_n are released. The transport layer deassembler and pattern checker are now active. The j204b_rx_link_valid asserts when the link is valid.
  11. Anytime you want to reset the design example, the reset can be applied through the PIO soft reset (hw_rst) or global_rst_n. The reset must be asserted when j204b_tx_rst_ack_n and j204b_rx_rst_ack_n are deasserted to 1. Asserting the reset puts the core PLL, JESD204B IP, and design example components into the reset state.

Avalon® Memory-Mapped Bridge

All the Avalon® memory-mapped submodules in the JESD204B subsystem are connected via Avalon® memory-mapped interconnect to a single Avalon® memory-mapped bridge. This bridge is the single interface for Avalon® memory-mapped communications into and out of the subsystem.

JTAG to Avalon® Master Bridge

The JTAG-to- Avalon® memory-mapped interface master bridge provides a connection between the JTAG host to access the memory-mapped JESD204B IP, GTS PMA, PIO control and status, Reset Sequencer control, and SPI Master module.

When the Avalon® memory-mapped interface domain is operating at the mgmt_clk domain, the mgmt_clk is required to be 2x faster than JTAG clock. The mgmt_clk is set to be 100 MHz in this design example.

The bridge consists of the following cores, which are available as standalone components in Platform Designer.
  • Avalon® Streaming Interface Serial Peripheral Interface and Avalon® Streaming Interface JTAG Interface—Accepts incoming data in bits and packs them into bytes.
  • Avalon® Streaming Interface Bytes to Packets Converter—Transforms packets into encoded stream of bytes, and a likewise encoded stream of bytes into packets.
  • Avalon® Streaming Interface Packets to Transactions Converter—Transforms packets with data encoded according to a specific protocol into Avalon® memory-mapped interface transactions, and encodes the responses into packets using the same protocol.
  • Avalon® Streaming Interface Single Clock FIFO—Buffers data from the Avalon® Streaming Interface JTAG Interface core. The FIFO is only used in the JTAG to Avalon® Master Bridge.

For the bridges to successfully transform the incoming streams of bytes to Avalon® memory-mapped interface transactions, the streams of bytes must be constructed according to the protocols used by the cores.

Note:
Do not use the master_write_from_file command when there is backpressure from the slave component to the master interface of the JTAG-to-master bridge component connected to it. Using the command during the backpressure can cause:
  • Data loss at the master interface
  • Command to run indefinitely with no response at the system console

The following figure shows how a bytestream changes through the different layers in the bridges.

Figure 9. JTAG to Avalon Master Bridge Core

JESD204B Platform Designer Address Map

Access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window. You can access the Avalon® memory-mapped interface slaves through the following address map.

Avalon® Memory-Mapped Interface Slave Component Address (32bit access, byte addressing)
JESD204B RX IP Core 0x000D_0000 – 0x000D_03FF
JESD204B TX IP Core 0x000C_0000 – 0x000C_03FF
Reset Sequencer 0 0x000E_0000 – 0x000E_00FF
Reset Sequencer 1 0x000E_0100 – 0x000E_01FF
GTS PMA AVMM 0x0100_0000 – 0x017F_FFFF
Core PLL reconfig 0x0201_0000 – 0x0201_03FF
SPI Control 0x0202_0000 – 0x0202_001F
PIO Control 0x0202_0020 – 0x0202_002F
PIO Status 0x0202_0040 – 0x0202_004F