GTS JESD204B Intel® FPGA IP Design Example User Guide

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ID 844839
Date 6/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide 2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204B Design Example 4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.5. Simulating the Design Example Testbench x
2.5.1. Simulation Testbench
3. Detailed Description for the GTS JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. GTS JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204B Design Example
4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide

2.3.1. Design Example Parameters

The GTS JESD204B Intel® FPGA IP parameter editor includes an Example Design tab for you to specify certain parameters before generating the design example.
Table 4.  Parameters in the Example Design Tab
Parameter Options Description
Select Design None (Default) No design examples selected.
System Console Control Design example with System Console control.
Simulation On/Off Turn on for the IP to generate the necessary files for simulating the design example.
Synthesis On/Off Turn on for the IP to generate the necessary files for Quartus® Prime compilation and hardware demonstration.
Enable Dual Simplex Generation On/Off Turn on to generate design example of the dual simplex version.
Note: Dual-Simplex Example Design supports duplex data path only. This is configured under the IP > Main tab.
JESD204B DS Wrapper Dual Simplex applied on JESD204B PHY Generate Example Design with applied Dual Simplex JESD204B IP with PHY layer only.
Dual Simplex applied on JESD204B Base PHY Generate Example Design with applied Dual Simplex JESD204B IP with Transport layer, Link layer and PHY layer.
HDL format (for simulation) Verilog (Default) Verilog HDL format for entire simulation fileset.
VHDL VHDL format for generated top-level wrapper file set.
HDL format (for synthesis) Verilog (Default) Verilog HDL format for synthesis fileset.
Generate 3-wire SPI module On/Off Turn on to enable 3-wire SPI interface instead of 4-wire SPI interface.
Select board None (Default) This option excludes hardware aspects for the design example. All the pin assignments are set to virtual pins.
Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) This option automatically selects the project’s target device to match the device on this development kit.
Test Pattern Enable internal serial loopback Select Internal Serial Loopback
Level Two Title