GTS JESD204B Intel® FPGA IP Design Example User Guide

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ID 844839
Date 6/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide 2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204B Design Example 4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.5. Simulating the Design Example Testbench x
2.5.1. Simulation Testbench
3. Detailed Description for the GTS JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. GTS JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204B Design Example
4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide

2.3. Generating the Design

To generate the design example from the IP parameter editor:

  1. Create a project targeting Agilex™ 5 or Agilex™ 3 device family and select a desired device.
  2. In the IP Catalog, Tools > IP Catalog, select GTS JESD204B Intel® FPGA IP .
  3. Specify a top-level name and the folder for your custom IP variation. This name identifies the IP variation files in your project. If prompted, also specify the target Altera FPGA device family. Click OK. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  4. Select a design from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design.
    Note: If you select another design, the settings of the IP parameters change accordingly.
  5. Under the Example Design tab, specify the design example parameters as described in Design Example Parameters. Select the desired development kit in the Select board parameter to generate the pin assignments in the .qsf file. Else, select None if you want to perform the pin assignments manually.
  6. If you require a dual simplex example design, enable the Enable Dual Simplex Generation option. Refer to Dual Simplex Design Example for more information on dual simplex mode.
  7. Click Generate Example Design.
The software generates all design files in the sub-directories. These files are required to run simulation and compilation.

Section Content
Design Example Parameters
Directory Structure

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