GTS JESD204B Intel® FPGA IP Design Example User Guide

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ID 844839
Date 6/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide 2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the GTS JESD204B Design Example 4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Dual Simplex Design Example 2.5. Simulating the Design Example Testbench 2.6. Compiling and Testing the Design Example
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
2.5. Simulating the Design Example Testbench x
2.5.1. Simulation Testbench
3. Detailed Description for the GTS JESD204B Design Example x
3.1. Supported Configurations 3.2. System Components 3.3. Design Example Clock and Reset 3.4. Design Example Signals 3.5. GTS JESD204B Design Example Status and Control Registers 3.6. Hardware Test for System Console Control Design Example
3.2. System Components x
3.2.1. JESD204B Subsystem in Platform Designer 3.2.2. Parallel I/O Core 3.2.3. Core PLL 3.2.4. SPI Master 3.2.5. Transport Layer 3.2.6. Test Pattern Generator 3.2.7. Test Pattern Checker
3.6. Hardware Test for System Console Control Design Example x
3.6.1. Board Connectivity
1. About the GTS JESD204B Intel® FPGA IP Design Example User Guide
2. GTS JESD204B Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the GTS JESD204B Design Example
4. Document Revision History for the GTS JESD204B Intel® FPGA IP Design Example User Guide

2.6. Compiling and Testing the Design Example

The JESD204B Intel® FPGA IP parameter editor allows you to run the design example on a target development kit.

Perform the following steps to compile the design and program the development board:

  1. Launch the Quartus® Prime software.
  2. In the Quartus® Prime software, open the Quartus® Prime project <example_design_directory>/ed_synth/intel_jesd204b_gts_ed_<data path>.qpf.
  3. Compile the design (Processing > Start Compilation).
    The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
  4. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
  5. Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
    Once downloaded, unzip the Installer Package to your PC. Navigate to the following path: agilex5e-prem-es-a5ed065bb32ae6sr0-v24-3-1b89-v1-0\examples\board_test_system
    Note: Build number and version may vary.
  6. To launch the Clock Controller GUI, launch the Board Test System application using one of the following scripts depending on your host OS:
    • Windows: start.bat
    • Linux: start.sh
    Note:

    On Windows systems, the start.bat script might be blocked and unable to run as it is an unrecognized app. You may need to adjust the properties of the .bat script to allow it to run. Right click on start.bat and click on Properties. Under the General tab, in the Security section, check the Unblock checkbox. Then click on OK. Rerun the start.bat.

    On Linux systems, make the start.sh script executable by running the following command in terminal: $ chmod 777 start.sh

  7. After the Board Test System application is launched, click on Clock to load the Clock Controller GUI.
    Table 7.  Clock Settings
    Clock Name Clock Frequency
    refclk_xcvr Select the frequency for the transceiver PLL reference clock in the IP parameter editor.
    refclk_core Select the frequency for the core PLL reference clock in the IP parameter editor.
    mgmt_clk 100 MHz
    Figure 7. Clock Control GUI SettingThis example shows the clock control GUI setting for a design example on a GTS device using the Agilex™ 5 E-Series Premium Development Kit.

    Note: For dual simplex example designs that require a reference clock frequency other than the default 153.6 MHz, the Si5518 clock chip needs to be programmed via a clock profile using the ClockBuilder Pro software.
  8. If you are performing external loopback test, attach the QSFP+ loopback module at cage QSFP2 (J13) for L=4 configuration. For L>4 configuration, attach another QSFP+ module at QSFP1 (J12).
  9. Configure the FPGA on the development board with the generated programming file (.sof file) using the Quartus® Prime Programmer.
To run the hardware testing using the Tcl script, refer to the Hardware Test for System Console Control Design Example section.
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