Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series

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ID 839365
Date 6/06/2025
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package B23D 2.3.2. Package B32B
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 5 D-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. DDR4 Interfaces 3.4.2.2. DDR5 Interfaces 3.4.2.3. LPDDR4 Interfaces 3.4.2.4. LPDDR5 Interfaces
3.7. Transceiver x
3.7.1. Migration Overview for Transceiver Application 3.7.2. GTS Transceiver Bank Name Change between Device Variant 3.7.3. GTS Transceiver Resources Count 3.7.4. Preserving Unused PMA Lanes
3.7.3. GTS Transceiver Resources Count x
3.7.3.1. Transceiver Resources and Lane Count 3.7.3.2. USB3.1 Hard IP 3.7.3.3. HVIO REFCLK Pin 3.7.3.4. CVP Requirement 3.7.3.5. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins 3.7.3.6. System PLL in Downbonded Quads 3.7.3.7. PERST Pin
3.7.3.5. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins x
3.7.3.5.1. GTS TX and GTS RX pin, and Reference Clock Pin 3.7.3.5.2. RCOMP_GTS Pins
3.8. Power x
3.8.1. Power Rails for Migration 3.8.2. Voltage Regulator Considerations for Agilex™ 5 Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 5 D-Series Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series

2.3.1. Package B23D

Figure 3. Consideration Details

The B23D package is available as Device Group A with Device Specification of C and D. All devices within this package support the same transceiver channel counts. Support for HPS depends on the Device Specification of the selected device. The considerations taken when migrating between this package depends on which Device Specification you are migrating to.

Refer to the following examples to understand the areas that require consideration when planning for migration within the B23D package.

Examples:
  • If you are migrating from Device Specification C of A5D025A to Device Specification D of A5D031A devices, then you are migrating from a non-HPS supported device to a HPS supported device.

The following table summarizes the areas that require consideration when planning migration within the B23D package. Refer to Functional Area for more details on each area.

Table 3.  B23D Package Consideration Requirement
Area Consideration Requirement
I/O No
LVDS SERDES Yes, refer to the LVDS SERDES section for more details.
Configuration No
EMIF No
MIPI No
HPS Yes, refer to the HPS section for more details.
Transceiver No
Power No
Sensor No
Related Information
HPS
Level Two Title