Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series

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ID 839365
Date 6/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package B23D 2.3.2. Package B32B
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 5 D-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. DDR4 Interfaces 3.4.2.2. DDR5 Interfaces 3.4.2.3. LPDDR4 Interfaces 3.4.2.4. LPDDR5 Interfaces
3.7. Transceiver x
3.7.1. Migration Overview for Transceiver Application 3.7.2. GTS Transceiver Bank Name Change between Device Variant 3.7.3. GTS Transceiver Resources Count 3.7.4. Preserving Unused PMA Lanes
3.7.3. GTS Transceiver Resources Count x
3.7.3.1. Transceiver Resources and Lane Count 3.7.3.2. USB3.1 Hard IP 3.7.3.3. HVIO REFCLK Pin 3.7.3.4. CVP Requirement 3.7.3.5. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins 3.7.3.6. System PLL in Downbonded Quads 3.7.3.7. PERST Pin
3.7.3.5. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins x
3.7.3.5.1. GTS TX and GTS RX pin, and Reference Clock Pin 3.7.3.5.2. RCOMP_GTS Pins
3.8. Power x
3.8.1. Power Rails for Migration 3.8.2. Voltage Regulator Considerations for Agilex™ 5 Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 5 D-Series Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs D-Series

3.1.1. HSIO

Direct migration using identical pin planning and location is supported when migrating between devices within package B23D and B32B because all devices within each of these packages have the same HSIO location availability. There is no change required to the VCCIO_PIO supply of these HSIO banks during migration.

Refer to the Agilex™ 5 Device Pin-Out Files for more information regarding the VCCIO_PIO pin location for Agilex™ 5 D-Series devices.

Refer to the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs for more information regarding HSIO bank feature and design guidelines for Agilex™ 5 D-Series devices.

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