Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

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ID 823097
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Functional Description 4. Interfaces 5. HAL Driver for DMA SoC Mode  6. Parameters 7. Registers 8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide
2. Introduction x
2.1. Device Family Support 2.2. Release Information 2.3. Resource Utilization
3. Functional Description x
3.1. DMA PCIe* Mode 3.2. DMA SoC Mode 3.3. Device Port 3.4. Prefetcher Engine 3.5. DMA Arbiter 3.6. DMA Router 3.7. CSRUnit 3.8. Descriptor Handling 3.9. Interrupts 3.10. Reset Initialization Flows 3.11. Transaction Flow
3.1. DMA PCIe* Mode x
3.1.1. Submodules
3.1.1. Submodules x
3.1.1.1. PCIe* TLP Constructor 3.1.1.2. PCIe* TLP ID Generation 3.1.1.3. PCIe TX Credit Controller 3.1.1.4. PCIe* TX Scheduler 3.1.1.5. PCIe TLP Completer 3.1.1.6. PCIe RX Router 3.1.1.7. PCIe* MSI-X Controller 3.1.1.8. PCIe BAR0 3.1.1.9. PCIe Bursting Manager (BAM) 3.1.1.10. Completion Timeout Parser 3.1.1.11. Control Shadow Parser
3.2. DMA SoC Mode x
3.2.1. Interrupt Controller 3.2.2. Host AXI-4 Agent 3.2.3. Host CSR AXI-4 Lite Agent
3.3. Device Port x
3.3.1. ST Source Agent/ST Sink Agent/MM Agent 3.3.2. Descriptor Engine 3.3.3. Agent Controller 3.3.4. Constructor 3.3.5. Responder 3.3.6. Width Adaptation FIFO
3.8. Descriptor Handling x
3.8.1. Link Descriptor 3.8.2. Data Descriptor 3.8.3. Responder Descriptor 3.8.4. Descriptor Chain 3.8.5. Aligned and Unaligned Transfer Support
3.8.2. Data Descriptor x
3.8.2.1. Data Descriptor - H2D Streaming Transfer 3.8.2.2. Data Descriptor - D2H Streaming Transfer 3.8.2.3. Data Descriptor - H2D Memory Transfer
3.8.3. Responder Descriptor x
3.8.3.1. Responder Descriptor - H2D Streaming Transfer 3.8.3.2. Responder Descriptor - D2H Streaming Transfer 3.8.3.3. Responder Descriptor - H2D Memory Transfer
3.8.4. Descriptor Chain x
3.8.4.1. Descriptor Fetch and Status Update Mechanism
3.11. Transaction Flow x
3.11.1. General DMA Operation Flow 3.11.2. Host to Device (H2D) Flow 3.11.3. Device to Host (D2H) Flow 3.11.4. Soft Reset Handshake Flow
4. Interfaces x
4.1. Port List 4.2. DMA PCIe* Mode Interfaces 4.3. DMA SoC Mode Interfaces 4.4. Device Port Interfaces 4.5. Resets 4.6. Clocks
4.2. DMA PCIe* Mode Interfaces x
4.2.1. Application Packet Receive Interface 4.2.2. Application Packet Transmit Interface 4.2.3. Control Shadow Interface 4.2.4. Transmit Flow Control Credit Interface 4.2.5. Completion Timeout Interface 4.2.6. PCIe* Miscellaneous Signals 4.2.7. Control and Status Register Responder Manager Interface 4.2.8. Bursting Manager Interface
4.3. DMA SoC Mode Interfaces x
4.3.1. Host AXI-4 Memory Map Manager Interface 4.3.2. Host AXI-4 Lite CSR Memory Map Subordinate Interface 4.3.3. Interrupt Interface
4.4. Device Port Interfaces x
4.4.1. Device to Host <PORT#> AXI-ST Subordinate Interface 4.4.2. Device to Host <PORT#> Avalon-ST Sink Interface 4.4.3. Host to Device <PORT#> AXI-ST Manager Interface 4.4.4. Host to Device <PORT#> Avalon-ST Source Interface 4.4.5. Host to Device <PORT#> AXI-4 Manager Interface
5. HAL Driver for DMA SoC Mode  x
5.1. Descriptor Indexing  5.2. HAL Public API 
5.1. Descriptor Indexing  x
5.1.1. Data Descriptors  5.1.2. Responders 
5.2. HAL Public API  x
5.2.1. Software Features 5.2.2. intel_ssgdma.c  5.2.3. intel_ssgdma_global.c 5.2.4. intel_ssgdma_device_port.c  5.2.5. intel_ssgdma_descriptor.c 
6. Parameters x
6.1. DMA Settings 6.2. Device Port Settings 6.3. DMA PCIe Mode Settings 6.4. DMA SoC Mode Settings 6.5. Example Design
6.2. Device Port Settings x
6.2.1. H2D MM 6.2.2. H2D ST 6.2.3. D2H ST
7. Registers x
7.1. Global CSR 7.2. MSI-X Memory Space 7.3. Device Port Control Register
1. Terms and Acronyms
2. Introduction
3. Functional Description
4. Interfaces
5. HAL Driver for DMA SoC Mode 
6. Parameters
7. Registers
8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

3.8.4. Descriptor Chain

The SSGDMA IP descriptors are formed in a block of contiguous 4k Bytes in host memory which can hold up to 128 descriptors where each descriptor is 32 bytes in size. The descriptor block starts with Link Descriptor which host the next block address that chain the block together. The descriptor block is also holding the number of descriptors present in the block. There is a maximum of 127 Data descriptors following the Link Descriptor.

The descriptor blocks can be chained in a loop from last descriptor block back to the first descriptor block via Link Descriptor per the maximum descriptor blocks in a queue configured in Q_SIZE register as in figure Descriptor Chain / Ring buffer for Descriptor Blocks (Continuous Ring). The hardware stops fetching from next new block when SSGDMA Q_EXTRACT_POINTER is equal to Q_INSERT_POINTER as in Descriptor Chain for Descriptor Blocks (Stop at Last Descriptor).

Figure 8. Descriptor Chain / Ring buffer for Descriptor Blocks (Continuous Ring)
Figure 9. Descriptor Chain for Descriptor Blocks (Stop at Last Descriptor)

The responder chain is required when Write-back is enabled for completion status update. A responder block contains 128 x256bits(32 bytes) responder. The SSGDMA IP is designed to have 128 blocks of Responder block, which in return support a maximum responder circular buffer of 128 blocks x 128 x 32 Bytes = 512kByes in size. Each responder block is chained in a manner where the base address of the descriptor block hosted in Responder Table (configurable via Q_RESPONDER_ADDR_L/H).

During the initialization of the queue, the driver needs to form the responder chain and fill up the physical address of the base offset for each block into Responder Table based on the maximum responder blocks configured in Q_RESP_SIZE. During the completion of each descriptor, the SSGDMA IP hardware writes the responder descriptor in sequence. On driver, it polls the " Complete" bit in the responder structure to determine if it is valid. Upon service the responder, it moves on to poll on the next responder's " Complete" bit.

Figure 10. Descriptor Chain for Responder Block
Note: Responder descriptors must not have descriptor IDX of 1 + (n*128), for example, 1, 129, 257, where n = 0, 1, 2,..., 254. These IDX values are dedicated for link descriptors.
The SSGDMA IP uses the concept of INSERT and EXTRACT pointers to keep track availability of descriptors in the ring buffer. When driver pushes descriptor to the ring buffer, the Q_INSERT_POINTER gets updated. Once the SSGDMA IP is done servicing the descriptor, the Q_EXTRACT_POINTER gets updated. With that, the driver can recycle the descriptor entry for new User Descriptor. All descriptors are served when Q_EXTRACT_POINTER is equal to Q_INSERT_POINTER. Otherwise, there are pending descriptors to be served. To avoid overrunning the Q_EXTRACT_POINTER, the driver should always check the availability of empty slot before sending descriptor to the queue.
Figure 11. Illustration of Ring Buffer and its Pointers

Section Content
Descriptor Fetch and Status Update Mechanism

Level Two Title