Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

Download PDF
ID 823097
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Functional Description 4. Interfaces 5. HAL Driver for DMA SoC Mode  6. Parameters 7. Registers 8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide
2. Introduction x
2.1. Device Family Support 2.2. Release Information 2.3. Resource Utilization
3. Functional Description x
3.1. DMA PCIe* Mode 3.2. DMA SoC Mode 3.3. Device Port 3.4. Prefetcher Engine 3.5. DMA Arbiter 3.6. DMA Router 3.7. CSRUnit 3.8. Descriptor Handling 3.9. Interrupts 3.10. Reset Initialization Flows 3.11. Transaction Flow
3.1. DMA PCIe* Mode x
3.1.1. Submodules
3.1.1. Submodules x
3.1.1.1. PCIe* TLP Constructor 3.1.1.2. PCIe* TLP ID Generation 3.1.1.3. PCIe TX Credit Controller 3.1.1.4. PCIe* TX Scheduler 3.1.1.5. PCIe TLP Completer 3.1.1.6. PCIe RX Router 3.1.1.7. PCIe* MSI-X Controller 3.1.1.8. PCIe BAR0 3.1.1.9. PCIe Bursting Manager (BAM) 3.1.1.10. Completion Timeout Parser 3.1.1.11. Control Shadow Parser
3.2. DMA SoC Mode x
3.2.1. Interrupt Controller 3.2.2. Host AXI-4 Agent 3.2.3. Host CSR AXI-4 Lite Agent
3.3. Device Port x
3.3.1. ST Source Agent/ST Sink Agent/MM Agent 3.3.2. Descriptor Engine 3.3.3. Agent Controller 3.3.4. Constructor 3.3.5. Responder 3.3.6. Width Adaptation FIFO
3.8. Descriptor Handling x
3.8.1. Link Descriptor 3.8.2. Data Descriptor 3.8.3. Responder Descriptor 3.8.4. Descriptor Chain 3.8.5. Aligned and Unaligned Transfer Support
3.8.2. Data Descriptor x
3.8.2.1. Data Descriptor - H2D Streaming Transfer 3.8.2.2. Data Descriptor - D2H Streaming Transfer 3.8.2.3. Data Descriptor - H2D Memory Transfer
3.8.3. Responder Descriptor x
3.8.3.1. Responder Descriptor - H2D Streaming Transfer 3.8.3.2. Responder Descriptor - D2H Streaming Transfer 3.8.3.3. Responder Descriptor - H2D Memory Transfer
3.8.4. Descriptor Chain x
3.8.4.1. Descriptor Fetch and Status Update Mechanism
3.11. Transaction Flow x
3.11.1. General DMA Operation Flow 3.11.2. Host to Device (H2D) Flow 3.11.3. Device to Host (D2H) Flow 3.11.4. Soft Reset Handshake Flow
4. Interfaces x
4.1. Port List 4.2. DMA PCIe* Mode Interfaces 4.3. DMA SoC Mode Interfaces 4.4. Device Port Interfaces 4.5. Resets 4.6. Clocks
4.2. DMA PCIe* Mode Interfaces x
4.2.1. Application Packet Receive Interface 4.2.2. Application Packet Transmit Interface 4.2.3. Control Shadow Interface 4.2.4. Transmit Flow Control Credit Interface 4.2.5. Completion Timeout Interface 4.2.6. PCIe* Miscellaneous Signals 4.2.7. Control and Status Register Responder Manager Interface 4.2.8. Bursting Manager Interface
4.3. DMA SoC Mode Interfaces x
4.3.1. Host AXI-4 Memory Map Manager Interface 4.3.2. Host AXI-4 Lite CSR Memory Map Subordinate Interface 4.3.3. Interrupt Interface
4.4. Device Port Interfaces x
4.4.1. Device to Host <PORT#> AXI-ST Subordinate Interface 4.4.2. Device to Host <PORT#> Avalon-ST Sink Interface 4.4.3. Host to Device <PORT#> AXI-ST Manager Interface 4.4.4. Host to Device <PORT#> Avalon-ST Source Interface 4.4.5. Host to Device <PORT#> AXI-4 Manager Interface
5. HAL Driver for DMA SoC Mode  x
5.1. Descriptor Indexing  5.2. HAL Public API 
5.1. Descriptor Indexing  x
5.1.1. Data Descriptors  5.1.2. Responders 
5.2. HAL Public API  x
5.2.1. Software Features 5.2.2. intel_ssgdma.c  5.2.3. intel_ssgdma_global.c 5.2.4. intel_ssgdma_device_port.c  5.2.5. intel_ssgdma_descriptor.c 
6. Parameters x
6.1. DMA Settings 6.2. Device Port Settings 6.3. DMA PCIe Mode Settings 6.4. DMA SoC Mode Settings 6.5. Example Design
6.2. Device Port Settings x
6.2.1. H2D MM 6.2.2. H2D ST 6.2.3. D2H ST
7. Registers x
7.1. Global CSR 7.2. MSI-X Memory Space 7.3. Device Port Control Register
1. Terms and Acronyms
2. Introduction
3. Functional Description
4. Interfaces
5. HAL Driver for DMA SoC Mode 
6. Parameters
7. Registers
8. Document Revision History for the Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

3.8.4.1. Descriptor Fetch and Status Update Mechanism

Follow these steps to initialize the SSGDMA IP:
  1. Issues soft reset to each device port through q_sw_reset_req in dedicated Q_CTRL register
  2. Issue soft reset the prefetcher through reset_prefetch_engine in CTRL register
Figure 12. Descriptor Fetch and Status Update Flow
The following steps illustrate SSGDMA flow in DMA PCIe mode, starting from software DMA request to data transfer completion:
  1. The User Application sends SSGDMA IP request to the SSGDMA driver.
  2. The SSGDMA Driver receives the request and translates the virtual memory of data buffer to physical memories that may fill up one or multiple descriptors. These descriptors goes to the intended descriptor queue. The driver then pack them into the descriptor block.
  3. The SSGDMA Driver updates the Q_INSERT_POINTER through PCIe link.
  4. When the SSGDMA Prefetcher Engine detects the change in the Q_INSERT_POINTER (updated by software) and Q_EXTRACT_POINTER (managed by Prefetcher Engine), the Prefetcher Engine triggers a read to the descriptor ring in host memory to get a block of descriptor.
  5. The block of descriptors dispatch into the H2D/D2H agent's descriptor FIFO.
  6. The agent's controller detects the presence of descriptor in the descriptor FIFO. The agent's controller reads a descriptor and execute the SSGDMA operation between the data in the host memory and user data. Once the SSGDMA operation completed, the responder gets constructed and get written to the Responder FIFO.
  7. The Prefetcher Engine arbitrates the responder requests from all agents. It retrieves the response from the Responder FIFO and writes the response to the SW Responder Queue if Write-back is enabled. The base address for each responder block is located at the Responder Table (configurable via Q_RESPONDER_ADDR_L/H). Every queue has its own table to host its responder queue addresses.
    Note: Responder write-back is optional and configurable via Q_CTRL registers.
  8. Upon service the responder, the Prefetcher Engine updates the Q_EXTRACT_POINTER based on the response received from the Agent.
  9. The following options is available for the driver to get the Completion status
    1. The Driver can poll for the Q_EXTRACT_POINTER to get the completion status, or
    2. Default option when write-back is enabled — The Driver can poll for the responder descriptor's Complete bit to see if the response is received. Under this mode, the driver can further decode the responder descriptor to get the detailed status of the operation.
  10. For DMA PCIe Mode, the following steps occur if the interrupt is enabled:
    1. The Prefetcher Engine generates the IRQ for the corresponding device port to MSI-X Controller upon receiving dummy completion on the successful write-back response transferred to host.
    2. The IRQ for each device agent are mapped to a dedicated pending bit from the PBA table. The corresponding pending bit is available upon receiving the IRQ from Prefetcher Engine.
    3. The MSI-X Controller detects the assertion of corresponding pending bit from PBA table, and it proceeds to retrieve the information for corresponding vector from the MSI-X table through CSR.
    4. The MSI-X Processor then setup a memory writes TLP with the corresponding message and address information retrieved from MSI-X Table to host provided if Mask bit is not set. Upon issued the memory write TLP, the MSI-X Processor proceeds to clear the corresponding pending bit from the PBA table.
  11. For DMA SoC Mode, the following steps occur if the interrupt is enabled:
    1. The Prefetcher Engine generates the IRQ for the corresponding device port to Interrupt Controller upon receiving dummy completion on the successful write-back response transferred to host.
    2. The Interrupt Controller combines all interrupt status for all device ports into a single interrupt that is connected to the Host. The irq bit of the STATUS register and the corresponding bit of the DEVICE_PORTS_IRQ_STATUS register of Global CSR is set, as well as the corresponding q_irq bits of Q_STATUS registers of Device Port CSR. Upon receiving the interrupt, the Driver polls for irq bit from the STATUS register and polls for DEVICE_PORTS_IRQ_STATUS register to identify which device port requires to be serviced. Then, the driver polls and clears the corresponding q_irq bits of the Device Port CSR registers. Before clearing the q_irq bit of Q_STATUS register, driver should update the Q_EXTRACT_POINTER_ACK to acknowledge that the descriptor has been serviced. This is to ensure that SSGDMA IP can assert the interrupt for descriptor completion by setting the q_desc_completion bit of Q_STATUS register correctly for pending descriptor to be served.

In the event if any unexpected issue or error scenario happened during the descriptor fetching or data fetching, the SSGDMA proceeds to terminate the operation. The write-back response from the corresponding device port is transferred to host and corresponding irq bits is asserted in the CSR registers.

Level Two Title