Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

ID 823097
Date 4/07/2025
Public
Document Table of Contents

4.3.1. Host AXI-4 Memory Map Manager Interface

This is the manager interface access host memory for descriptors and data. Supporting AXI-4 interface.

Clock Domain: host_clk

Reset: host_aresetn

Table 45.  Host AXI-4 Interface
Signal Name Direction Description
Write Address Channel
host_awvalid OUT Indicates that the write address channel signals are valid
host_awready IN Indicates that a transfer on the write address channel can be accepted

host_awaddr

[HOST_AWD-1:0]

OUT

The address of the first transfer in a write transaction

The default value of HOST_AWD = 64

host_awlen

[HOST_LWD-1:0]

OUT

Length, the exact number of data transfers in a write transaction

The default value of HOST_LWD = 8

host_awburst[1:0] 2

OUT The burst type of data transfers in a write transaction.

host_awsize

[2:0]

OUT The maximum number of bytes to transfer in each data transfer, or beat, in a burst
host_awprot[2:0] OUT Protection attributes of a write transaction: privilege, security level, and access type
host_awid[HOST_IDWD-1:0] OUT

Identification tag for a write transaction

The default value of HOST_IDWD = 5

host_awcache[3:0] OUT Indicates how a write transaction is required to progress through a system
Write Data Channel
host_wvalid OUT Indicates that the write data channel signals are valid
host_wlast OUT Indicates whether this is the last data transfer in a write transaction
host_wready IN Indicates that a transfer on the write data channel can be accepted

host_wdata

[HOST_DWD -1:0]

OUT

Write Data

The default value of HOST_DWD = 256

host_wstrb

[HOST_DWD /8-1:0]

OUT Write strobes, indicate which byte lanes hold valid data
Write Response Channel
host_bvalid IN Indicates that the write response channel signals are valid
host_bready OUT Indicates that a transfer on the write response channel can be accepted
host_bresp[1:0] IN Write response, indicates the status of a write transaction
host_bid[HOST_IDWD-1:0] IN

Identification tag for a write response

The default value of HOST_IDWD = 5

Read Address Channel
host_arvalid OUT Indicates that the read address channel signals are valid
host_arready IN Indicates that a transfer on the read address channel can be accepted

host_araddr

[HOST_AWD-1:0]

OUT

The address of the first transfer in a read transaction

The default value of HOST_AWD = 64

host_arlen

[HOST_LWD-1:0]

OUT

Length, the exact number of data transfers in a read transaction

The default value of HOST_LWD = 8

host_arburst[1:0]2

OUT The burst type of data transfers in a read transaction.

host_arsize

[2:0]

OUT The maximum number of bytes to transfer in each data transfer, or beat, in a burst
host_arprot[2:0] OUT Protection attributes of a read transaction: privilege, security level, and access type
host_arid[HOST_IDWD-1:0] OUT

Identification tag for a read transaction

The default value of HOST_IDWD = 5

host_arcache[3:0] OUT Indicates how a read transaction is required to progress though a system
Read Data Channel
host_rvalid IN Indicates that the read data channel signals are valid
host_rlast IN Indicates whether this is the last data transfer in a read transaction
host_rready OUT Indicates that a transfer on the read data channel can be accepted

host_rdata

[HOST_DWD-1:0]

IN

Read data

The default value of HOST_DWD = 256

host_rresp

[1:0]

IN Read response, indicates the status of a read transfer
host_rid[HOST_IDWD-1:0] IN

Identification tag for a read response

The default value of HOST_IDWD = 5

2 Only incrementing(INCR - 2'b1) burst is supported in initial phase.