GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 8/04/2025
Public
Document Table of Contents

2.6.3.1. I/O PLL in HVIO Bank as System PLL

Below the GTS transceiver banks, there are two HVIO banks (5A/5B or 6A/6B) that share a common I/O PLL. This I/O PLL can be used as a second system PLL.
Note: The current release of the Quartus® Prime Pro Edition software has limited support for this mode. It is enabled for the GTS Ethernet Hard IP with specific configurations and the PMA Direct mode. Refer to the GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs for more information.
For certain devices, there is only one GTS transceiver bank and therefore only one system PLL is available. The following devices have only one GTS transceiver bank and one system PLL:
  • A5E 008
  • A5E 013
The two HVIO banks that are adjacent to the GTS transceiver bank 1A are:
  • HVIO bank 5A
  • HVIO bank 5B
The input reference clock for the I/O PLL can come from any one of the following four pins in the HVIO banks 5A or 5B:
  • PLLREFCLK1 (5A)
  • PLLREFCLK2 (5A)
  • PLLREFCLK1 (5B)
  • PLLREFCLK2 (5B)
The two HVIO banks that are adjacent to the GTS transceiver bank 4A are:
  • HVIO bank 6A
  • HVIO bank 6B
The input reference clock for the I/O PLL can come from any one of the following four pins in the HVIO banks 6A or 6B:
  • PLLREFCLK1 (6A)
  • PLLREFCLK2 (6A)
  • PLLREFCLK1 (6B)
  • PLLREFCLK2 (6B)

You must consider the following when using the I/O PLL. As the I/O PLL is different from the system PLL, you have to instantiate the I/O PLL using the IOPLL IP instead of the GTS System PLL Clocks IP. Refer to the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs for more information. The I/O PLL in the slowest device speed grade is not capable of reaching the system PLL's maximum frequency of 1000 MHz. Refer to the device datasheet for the I/O PLL specifications. Additionally, the I/O PLL does not support the fractional mode.