GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817660
Date 10/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY IP 4. Implementing the GTS System PLL Clocks IP 5. Implementing the GTS Reset Sequencer IP 6. GTS PMA/FEC Direct PHY IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit A. Transceiver Toolkit Helper Script 9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. CPRI 2.1.1.1.4. GPON 2.1.1.1.5. OTN 2.1.1.1.6. SATA/SAS
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.2.3. Unused PMA Rules x
2.2.3.1. Unused PMA Not Planned for Use in the Future 2.2.3.2. Unused PMA Planned for Use in the Future
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. RX PMA Tuning 2.3.2.5. RX PMA Equalization Modes
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.3.2.5. RX PMA Equalization Modes x
2.3.2.5.1. RX Auto Adaptation Mode 2.3.2.5.2. RX Manual Equalization Mode 2.3.2.5.3. RX Native Adaptation Mode
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLL in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
2.7.1. Bonding Architecture x
2.7.1.1. PCS Configuration: Tx and Rx Datapaths
3. Implementing the GTS PMA/FEC Direct PHY IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY IP 3.3. Configuring the GTS PMA/FEC Direct PHY IP 3.4. Dynamically Reconfigurable PHY 3.5. Signal and Port Reference 3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.7. Clocking 3.8. Custom Cadence Generation Ports and Logic 3.9. Asserting Reset 3.10. Bonding Implementation 3.11. Configuration Register 3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing 3.13. Configurable Quartus® Prime Software Settings 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Mode and Common Datapath Options 3.3.3. Dynamically Reconfigurable PHY Settings 3.3.4. TX Datapath Options 3.3.5. RX Datapath Options 3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.7. FEC Options 3.3.8. PCS Options 3.3.9. Avalon® Memory-Mapped Interface Options 3.3.10. Register Map IP-XACT Support 3.3.11. Analog Parameter Options
3.3.4. TX Datapath Options x
3.3.4.1. TX PMA Interface Parameters
3.3.5. RX Datapath Options x
3.3.5.1. RX PMA Interface Parameters
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.6.1. PMA Configuration Rules for SDI Mode 3.3.6.2. PMA Configuration Rules for HDMI Mode 3.3.6.3. PMA Configuration Rules for CPRI Mode 3.3.6.4. PMA Configuration Rules for GPON Mode 3.3.6.5. PMA Configuration Rules for OTN Mode 3.3.6.6. PMA Configuration Rules for SATA/SAS Mode
3.3.11. Analog Parameter Options x
3.3.11.1. User Guidelines for Setting the TX Equalizer in Loopback Mode
3.4. Dynamically Reconfigurable PHY x
3.4.1. Clock Generation and Constraints for Multiple Profiles Design
3.5. Signal and Port Reference x
3.5.1. TX and RX Parallel and Serial Interface Signals 3.5.2. TX and RX Reference Clock and Clock Output Interface Signals 3.5.3. Reset Signals 3.5.4. FEC Signals 3.5.5. Custom Cadence Control and Status Signals 3.5.6. TX PMA Control Signals 3.5.7. RX PMA Status Signals 3.5.8. TX and RX PMA and Core Interface FIFO Signals 3.5.9. Avalon Memory-Mapped Interface Signals
3.7. Clocking x
3.7.1. Clock Ports 3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.7.4. PMA Fractional Mode 3.7.5. Input Reference Clock Buffer Protection 3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.7.5. Input Reference Clock Buffer Protection x
3.7.5.1. Buffer Turn-on Request via Register Method 3.7.5.2. Buffer Turn-on Request via Status and Control Ports Method
3.8. Custom Cadence Generation Ports and Logic x
3.8.1. Implementing PMA Direct Mode with TX Core FIFO in Elastic Configuration 3.8.2. Enabling the i_tx_cadence_slow_clk_locked Port
3.9. Asserting Reset x
3.9.1. Reset Signal Requirements 3.9.2. Power On Reset Requirements 3.9.3. Reset Signals—Block Level 3.9.4. Run-time Reset Sequence—TX 3.9.5. Run-time Reset Sequence—RX 3.9.6. Run-time Reset Sequence—TX + RX 3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.9.8. TX PLL Lock Loss
3.10. Bonding Implementation x
3.10.1. Bonding Placement Requirements 3.10.2. Multilane RX Simplex Implementation
3.11. Configuration Register x
3.11.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. GTS PMA Register Map 3.11.3. Accessing Configuration Registers 3.11.4. Configuration Registers for the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY
3.11.2. GTS PMA Register Map x
3.11.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.11.3. Accessing Configuration Registers x
3.11.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.11.3.2. Accessing GTS PMA Registers
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing x
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP 3.12.2. Using JTAG to Avalon Master Bridge IP
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP x
3.12.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.12.2. Using JTAG to Avalon Master Bridge IP x
3.12.2.1. RTL Connection Example for JTAG to Avalon Master Bridge IP
3.13. Configurable Quartus® Prime Software Settings x
3.13.1. Configuring the RX Adaptation Mode and PMA Manual Tuning
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. Direct Register Method 3.14.2. GTS Attribute Access Method
3.14.1. Direct Register Method x
3.14.1.1. Direct Register Method Examples
3.14.2. GTS Attribute Access Method x
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode) 3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Equalization Mode) 3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA 3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
4. Implementing the GTS System PLL Clocks IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer IP General Interface 5.5. GTS Reset Sequencer IP Design Flow 5.6. GTS Reset Sequencer IP Use Cases 5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP
5.6. GTS Reset Sequencer IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY IP 6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design 6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY IP Example Design 6.7. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design 6.8. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design 6.9. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description 6.10. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench 6.11. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design 6.12. Hardware Testing the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
6.8. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design x
6.8.1. Fast Simulation Support 6.8.2. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Directory Structure
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Altera FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
A. Transceiver Toolkit Helper Script x
A.1. Introduction A.2. Executing the Script
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
A. Transceiver Toolkit Helper Script
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

3.5. Signal and Port Reference

The following section describes all GTS PMA/FEC Direct PHY IP ports and signals.

Each tx_parallel_data and rx_parallel_data bus is exposed as 80 bits per lane. Some bits map to special functionality.

Each TX and RX PMA interface has 80 bits on the parallel data interface. The determination of active and inactive ports depends on specific configuration parameters, such as the number of lanes and the PMA width.

For details about mapping of data and control signals, refer to Parallel Data Mapping Information.

When you enable the Provide separate interface for each PMA option for the GTS PMA/FEC Direct PHY IP, the PHY presents separate data and clock interfaces for each PMA lane, rather than a wide bus. Each PMA lane signal name is appended with a _xcvr<n> suffix, with n = PMA index number. When Provide separate interface for each PMA is disabled, the signal name does not append _xcvr<n>.

For example, if you enable Provide separate interface for each PMA for two PMA lane configuration, the serial port signal names appear as:

o_tx_serial_data_xcvr0, o_tx_serial_data_xcvr1.

If you disable Provide separate interface for each PMA for two lane PMA configuration, the serial port signal name appears as: o_tx_serial_data[1:0].

The following are the signals that do not have separate interfaces when Provide separate interface for each PMA option is on:

  • i_system_pll_clk
  • i_tx_reset, i_rx_reset, o_tx_reset_ack, o_rx_reset_ack, o_tx_ready, o_rx_ready
  • rsfec signals
  • i_tx_cadence_fast_clk, i_tx_cadence_slow_clk, i_tx_cadence_slow_clk_locked
Note: When the Enable FEC option is on, a separate interface is not available for each PMA by use of the Provide separate interface for each PMA option.
Table 43.   Variables Defining Bits for the Interfacing Ports in Port and Signal Reference
Variable Values Description
<N>

1, 2, 4, 6, 8

 N is the number of PMA lanes.
<n> 0 to N-1 n is the PMA index number.
<X>

X=1

 X is 1 always.
<M> 0 to M-1 M is the number of banks per side of the device.
<K p >

Ceiling(log2(N))

K p = 0, 1, 2, 3, 4

K p is the PMA reconfiguration interface address.

K p =0 if separate Avalon® interface per PMA is enabled

K p =Ceiling(log2(N) if separate Avalon® interface per PMA is disabled.

Section Content
TX and RX Parallel and Serial Interface Signals
TX and RX Reference Clock and Clock Output Interface Signals
Reset Signals
FEC Signals
Custom Cadence Control and Status Signals
TX PMA Control Signals
RX PMA Status Signals
TX and RX PMA and Core Interface FIFO Signals
Avalon Memory-Mapped Interface Signals

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