Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 4/01/2024
Public

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2.12. Timing/Power Optimization Feature in M20K Blocks

The timing/power optimization feature in the M20K blocks in Agilex™ 5 devices allows you to select High Speed (HS) mode or Low Power (LP) mode.
  • High Speed (HS) mode—Provides the best performance of the M20K blocks.
  • Low Power (LP) mode—Reduces static power consumption if the M20K blocks do not need to be high performance.
Note: You can select the timing/power optimization feature in the parameter editors of the RAM/ROM IP cores. This option is only applicable when you select the M20K memory type on Agilex™ 5 devices.