Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 4/01/2024
Public

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1.1. Agilex™ 5 Embedded Memory Features

The Agilex™ 5 devices contain the following types of memory blocks: M20K blocks, and memory logic array blocks (MLABs).
  • 20-kilobit (Kb) M20K blocks
    • Blocks of dedicated memory resources.
    • Ideal for larger memory arrays, while providing a large number of independent ports.
  • 640-bit MLABs
    • Memory blocks configured from dual-purpose logic array blocks (LABs).
    • Ideal for wide and shallow memory arrays.
    • Optimized for implementation of shift registers for digital signal processing (DSP) applications, wide and shallow FIFO buffers, and filter delay lines.
    • Each MLAB is made up of ten adaptive logic modules (ALMs).

In Agilex™ 5 devices, you can configure each ALM in the MLAB as ten 32×2 blocks. The Agilex™ 5 devices provide one 32×20 simple dual-port SRAM block per MLAB.

The Agilex™ 5 embedded memory blocks support the following operation modes:
  • Single-port
  • Simple dual-port
  • True dual-port
  • Simple quad-port
  • ROM
Table 1.   Agilex™ 5 Embedded Memory FeaturesThis table summarizes the features supported by the Agilex™ 5 embedded memory blocks.
Features M20K MLAB
Maximum operating frequency
  • 1 GHz (simple dual-port RAM mode)
  • 600 MHz (true dual-port and simple quad-port RAM mode)

850 MHz

Total RAM bits (including parity bits) 20,480 bits 640 bits
Byte enable Supported Supported
Address clock enable

(address stall)

Supported (only in simple dual-port RAM mode) Supported
Simple dual-port mixed width Supported N/A
FIFO buffer mixed width Supported N/A
Memory Initialization File (.mif) Supported Supported
Dual-clock mode Supported (only in simple dual-port RAM mode) Supported
Full synchronous memory Supported Supported
Asynchronous memory N/A Only for flow-through read memory operations
Power-up state Output ports are cleared
  • Registered output ports are cleared
  • Unregistered output ports read memory contents
Asynchronous/Synchronous Clears
  • Output registers and output latches
  • Supports asynchronous clear on read address registers (only in simple dual-port and simple quad-port modes)
Output registers and output latches
Write/read operation triggering Rising clock edges Rising clock edges
Same-port read-during-write
  • Single Port RAM: Output ports set to Old Data or Don't Care
  • True Dual Port RAM: Output ports set to New Data
  • Simple Quad Port: Output ports set to Don't Care
Output ports set to Don't Care
Mixed-port read-during-write
  • Simple Dual Port RAM: Output ports set to Old Data or Don't Care
  • True Dual Port RAM: Output ports set to Don't Care
  • Simple Quad Port: Output ports set to new_a_old_b
Output ports set to New Data, Old Data, or Don't Care
Error Correction Code (ECC) support
  • Built-in support ×32-wide simple dual-port mode
  • Parity bits

N/A

Force-to-Zero Supported N/A
Coherent read memory Supported N/A
Freeze logic Supported N/A
True dual port (TDP) dual clock emulator Supported N/A