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1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.2.1. Release Information for FIFO Intel® FPGA IP
4.2.2. Configuration Methods
4.2.3. Specifications
4.2.4. FIFO Functional Timing Requirements
4.2.5. SCFIFO ALMOST_EMPTY Functional Timing
4.2.6. FIFO Output Status Flag and Latency
4.2.7. FIFO Metastability Protection and Related Options
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.9. SCFIFO and DCFIFO Show-Ahead Mode
4.2.10. Different Input and Output Width
4.2.11. DCFIFO Timing Constraint Setting
4.2.12. Coding Example for Manual Instantiation
4.2.13. Instantiation Template
4.2.14. Design Example
4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.16. Guidelines for Embedded Memory ECC Feature
4.2.17. FIFO Intel® FPGA IP Parameters
4.2.18. Reset Scheme
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.3.5. Shift Register Ports and Parameters Setting
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4.2.13. Instantiation Template
DCFIFO Verilog HDL Instantiation Template
//Quartus Prime Parameterizable Macro Template //ASYNC FIFO //Macro Location : //$QUARTUS_ROOTDIR/libraries/megafunctions/async_fifo.v async_fifo #( .DATA_WIDTH_A (8), .ADDR_WIDTH_A (11), .DATA_WIDTH_B (8), .ADDR_WIDTH_B (11), .RDSYNC_DELAYPIPE (2), .WRSYNC_DELAYPIPE (2), .ENABLE_SHOWAHEAD ("OFF"), .UNDERFLOW_CHECKING ("ON"), .OVERFLOW_CHECKING ("ON"), .ADD_USEDW_MSB_BIT ("OFF"), .WRITE_ACLR_SYNCH ("OFF"), .READ_ACLR_SYNCH ("OFF"), .ADD_RAM_OUTPUT_REGISTER ("OFF"), .RAM_BLOCK_TYPE ("M20K"), .MAXIMUM_DEPTH (2048), .BYTE_EN_WIDTH (1), .BYTE_SIZE (8) ) <instance_name> ( .data (_connected_to_data_), .rdclk (_connected_to_rdclk_), .wrclk (_connected_to_wrclk_), .aclr (_connected_to_aclr_), .rdreq (_connected_to_rdreq_), .wrreq (_connected_to_wrreq_), .byteena (_connected_to_byteena_), .rdfull (_connected_to_rdfull_), .wrfull (_connected_to_wrfull_), .rdempty (_connected_to_rdempty_), .wrempty (_connected_to_wrempty_), .rdusedw (_connected_to_rdusedw_), .wrusedw (_connected_to_wrusedw_), .q (_connected_to_q_) );
DCFIFO VHDL Instantiation Template
-- Macro Location : -- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd -- Add the library and use clauses before the design unit declaration library altera_lnsim; use altera_lnsim.altera_lnsim_components.all; -- Instantiating ASYNC_FIFO <instance_name> : ASYNC_FIFO generic map ( DATA_WIDTH_A => 8, ADDR_WIDTH_A => 11, DATA_WIDTH_B => 8, ADDR_WIDTH_B => 11, RDSYNC_DELAYPIPE => 2, WRSYNC_DELAYPIPE => 2, ENABLE_SHOWAHEAD => "OFF", UNDERFLOW_CHECKING => "ON", OVERFLOW_CHECKING => "ON", ADD_USEDW_MSB_BIT => "OFF", WRITE_ACLR_SYNCH => "OFF", READ_ACLR_SYNCH => "OFF", ADD_RAM_OUTPUT_REGISTER => "OFF", RAM_BLOCK_TYPE => "M20K", MAXIMUM_DEPTH => 2048, BYTE_EN_WIDTH => 1, BYTE_SIZE => 8 ) port map ( data => _connected_to_data_, -- input, width = DATA_WIDTH_A rdclk => _connected_to_rdclk_, -- input, width = 1 wrclk => _connected_to_wrclk_, -- input, width = 1 aclr => _connected_to_aclr_, -- input, width = 1 rdreq => _connected_to_rdreq_, -- input, width = 1 wrreq => _connected_to_wrreq_, -- input, width = 1 byteena => _connected_to_byteena_, -- input, width = BYTE_EN_WIDTH rdfull => _connected_to_rdfull_, -- output, width = 1 wrfull => _connected_to_wrfull_, -- output, width = 1 rdempty => _connected_to_rdempty_, -- output, width = 1 wrempty => _connected_to_wrempty_, -- output, width = 1 rdusedw => _connected_to_rdusedw_, -- output, width = ADDR_WIDTH_B wrusedw => _connected_to_wrusedw_, -- output, width = ADDR_WIDTH_A q => _connected_to_q_ -- output, width = DATA_WIDTH_B };
SCFIFO Verilog HDL Instantiation Template
//Quartus Prime Parameterizable Macro Template //SYNC FIFO //Macro Location : //$QUARTUS_ROOTDIR/libraries/megafunctions/sync_fifo.v sync_fifo #( .ADD_RAM_OUTPUT_REGISTER ("OFF"), .ALMOST_EMPTY_VALUE (1), .ALMOST_FULL_VALUE (1), .ENABLE_SCLR ("OFF"), .ENABLE_ACLR ("OFF"), .RAM_BLOCK_TYPE ("M20K"), .ALLOW_RWCYCLE_WHEN_FULL ("ON"), .ENABLE_SHOWAHEAD ("OFF"), .DATA_WIDTH (8), .ADDR_WIDTH (11), .OVERFLOW_CHECKING ("ON"), .UNDERFLOW_CHECKING ("ON"), .MAXIMUM_DEPTH (2048), .BYTE_SIZE (8), .BYTE_EN_WIDTH (1) ) <instance_name> ( .clock (_connected_to_clock_), //input, width = 1 .data (_connected_to_data_), //input, width = DATA_WIDTH .rdreq (_connected_to_rdreq_), //input, width = 1 .sclr (_connected_to_sclr_), //input, width = 1, synch reset .aclr (_connected_to_aclr_), //input, width = 1, asynch reset .wrreq (_connected_to_wrreq_), //input, width = 1 .byteena (_connected_to_byteena_), //input, width = BYTE_EN_WIDTH .almost_empty (_connected_to_almost_empty_), //output, width = 1 .almost_full (_connected_to_almost_full_), //output, width = 1 .q (_connected_to_q_), //output, width = DATA_WIDTH .usedw (_connected_to_usedw_), //output, width = ADDR_WIDTH .empty (_connected_to_empty_), //output, width = 1 .full (_connected_to_full_) //output, width = 1 );
SCFIFO VHDL Instantiation Template
-- Macro Location : -- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd -- Add the library and use clauses before the design unit declaration library altera_lnsim; use altera_lnsim.altera_lnsim_components.all; -- Instantiating SYNC_FIFO <instance_name> : SYNC_FIFO generic map ( ADD_RAM_OUTPUT_REGISTER => "OFF", ALMOST_EMPTY_VALUE => 1, ALMOST_FULL_VALUE => 1, ENABLE_SCLR => "OFF", ENABLE_ACLR => "OFF", RAM_BLOCK_TYPE => "M20K", ALLOW_RWCYCLE_WHEN_FULL => "ON", ENABLE_SHOWAHEAD => "OFF", DATA_WIDTH => 8, ADDR_WIDTH => 11, OVERFLOW_CHECKING => "ON", UNDERFLOW_CHECKING => "ON", MAXIMUM_DEPTH => 2048, BYTE_SIZE => 8, BYTE_EN_WIDTH => 1 ) port map ( clock => _connected_to_clock_, -- input, width = 1 data => _connected_to_data_, -- input, width = DATA_WIDTH rdreq => _connected_to_rdreq_, -- input, width = 1 sclr => _connected_to_sclr_, -- input, width = 1 aclr => _connected_to_aclr_, -- input, width = 1 wrreq => _connected_to_wrreq_, -- input, width = 1 byteena => _connected_to_byteena_, -- input, width = BYTE_EN_WIDTH empty => _connected_to_empty_, -- output, width = 1 full => _connected_to_full_, -- output, width = 1 almost_empty => _connected_to_almost_empty_, -- output, width = 1 almost_full => _connected_to_almost_full_, -- output, width = 1 q => _connected_to_q_, -- output, width = DATA_WIDTH usedw => _connected_to_usedw_ -- output, width = ADDR_WIDTH );