Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 4/01/2024
Public

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2.5.4. Asynchronous/Synchronous Clears in Clocking Modes

In all clocking modes, asynchronous and synchronous clears are available only for output latches and output registers.

In all clocking modes, asynchronous clear is available for read address registers on simple dual-port and simple quad-port modes.