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1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.2.1. Release Information for FIFO Intel® FPGA IP
4.2.2. Configuration Methods
4.2.3. Specifications
4.2.4. FIFO Functional Timing Requirements
4.2.5. SCFIFO ALMOST_EMPTY Functional Timing
4.2.6. FIFO Output Status Flag and Latency
4.2.7. FIFO Metastability Protection and Related Options
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.9. SCFIFO and DCFIFO Show-Ahead Mode
4.2.10. Different Input and Output Width
4.2.11. DCFIFO Timing Constraint Setting
4.2.12. Coding Example for Manual Instantiation
4.2.13. Instantiation Template
4.2.14. Design Example
4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.16. Guidelines for Embedded Memory ECC Feature
4.2.17. FIFO Intel® FPGA IP Parameters
4.2.18. Reset Scheme
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.3.5. Shift Register Ports and Parameters Setting
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4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
This table lists the parameters for the ROM: 1-PORT Intel® FPGA IP.
Parameter | Legal Values | Description | |
---|---|---|---|
Parameter Settings: General Page | |||
How wide should the ‘q’ output bus be? | — | Specifies the width of the ‘q’ output bus. | |
How many words of memory? | — | Specifies the number of words. | |
What should the memory block type be? | Auto, MLAB, M20K | Specifies the memory block type. The types of memory block that are available for selection depends on your target device. | |
Set the maximum block depth to |
|
Specifies the maximum block depth in words. | |
Which clocking method would you like to use? |
|
Specifies the clocking method to use.
|
|
Parameter Settings: Regs/Clken/Aclrs | |||
Which ports should be registered?
The following options are available:
|
On/Off | Specifies whether to register the input and output ports. | |
Use clock enable for port A input registers | On/Off | Specifies whether to use clock enable for port A input registers. | |
Use clock enable for port A output registers | On/Off | Specifies whether to use clock enable for port A output registers. | |
Create an ‘addressstall_a’ input port | On/Off | Specifies whether to create an addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers. | |
Create an ‘aclr’ asynchronous clear for the registered ports. The following options are available:
|
On/Off | Specifies whether the registered ports be affected by an asynchronous clear port. | |
Create a ‘sclr’ asynchronous clear for the registered ports.
|
On/Off | Specifies whether the q port be affected by a synchronous clear port. | |
Create an ‘rden’ read enable signal | On/Off | Specifies whether to create a read enable signal. | |
Parameter Settings: Mem Init | |||
Do you want to specify the initial content of the memory? |
|
Specifies the initial content of the memory. In ROM mode, you must specify a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex). The Yes, use this file for the memory content data option is turned on by default. |
|
Parameter Settings: Performance Optimization | |||
Enable Force-to-Zero | On/Off | Specifies whether to set the output to zero when you deassert the read enable signal. Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block. |
|
Which timing/power optimization option do you want to use? |
|
Specifies the timing/power optimization option to use. This option is only applicable when you select M20K memory type on Agilex™ 5 devices. |