High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 4/21/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1. Release Information

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel® Quartus® Prime software version to another. A change in:

  • X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 1.  
Item Description
IP Version 1.2.0
Intel® Quartus® Prime 23.1
Release Date 2023.04.21
Note: This documentation is preliminary and subject to change.
Note: Device support for Intel Agilex® 7 M-series FPGAs and SoCs in the Intel® Quartus® Prime Pro Edition software version 23.1 is restricted. To enable M-series device support in your instance of the Intel® Quartus® Prime Pro Edition software, contact your regional Intel FPGA sales representative.