High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 4/21/2023

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3.4. Intel Agilex® 7 M-Series UIB Architecture

The Intel Agilex® 7 M-Series device architecture includes the universal interface bus (UIB) subsystem (UIBSS) which contains the necessary logic to interface the HBM controller's NoC targets to the HBM2E DRAM. The UIB subsystem is designed to be compatible with the HBM2E DRAM standard.

Each UIB subsystem includes the HBM2E hardened controller and the universal interface bus, consisting of the hardened physical interface and I/O logic needed to interface to each HBM2E DRAM device. The NoC initiators and targets interface to the core logic and HBM2E controllers using the AMBA AXI4 protocol.

The following figure shows a high-level block diagram of the UIB subsystem. The UIB subsystem includes the following hardened blocks:

  • HBM2E memory controller (HBMC).
  • UIB PHY, including the UIB physical layer and I/O.
  • A block that is responsible for initializing the UIB hardware, including configuration of the HBMC, calibration of the HBM memory interface, and sequencing of hardware resets.
Figure 4. Block Diagram of Intel Agilex® 7 M-Series HBM2E Implementation

The user core clock drives the logic highlighted in green, while the UIB clocks the logic highlighted in blue. The UIB clock also drives the HBM2E interface clock.

Channel Mapping

Each HBM2E DRAM supports eight channels, each comprising two pseudo-channels. The table below shows the mapping from the HBM2E DRAM channels to the HBM controller channels, from controller channels to IP GUI channel names.

Table 2.  Channel Mapping
HBM2E IP GUI Channel AXI4 Channel (HBMC) HBM2E DRAM Channel
Channel 0 ch0_u0 Channel E
Channel 1 ch1_u0 Channel F
Channel 2 ch2_u0 Channel A
Channel 3 ch3_u0 Channel B
Channel 4 ch4_u0 Channel G
Channel 5 ch5_u0 Channel H
Channel 6 ch6_u0 Channel C
Channel 7 ch7_u0 Channel D


The following table lists the HBM2E signals that interface to the UIB. The UIB drives the HBM2E signals and decodes the received data from the HBM2E. These signals cannot be accessed through the AXI4 User Interface.

Table 3.  Summary of Per-channel Signals
Signal Name Signal Width Notes
Data 128 128 bit bidirectional DQ per channel
Column command/address 9 9-bit wide column address bits
Row command/address 7 7-bit wide row address bits
DBI 16 1 DBI per 8 DQs
DM_CB 16 1 DM per 8 DQs. You can use these pins for DM or ECC, but not both.
PAR 4 1 parity bit per 32 DQs
DERR 4 1 data error bit per 32 DQs
Strobes 16 Separate strobes for read and write strobes. One differential pair per 32 DQs for read and write.
Clock 2 Clocks address and command signals
CKE 1 Clock enable
AERR 1 Address error

(You can see the above signals in simulation.)

The following table lists the HBM2E signals that are common to all Pseudo Channels in each HBM2E interface.

Table 4.  Summary of Global HBM2E Signals
Signal Name Signal Width Notes
Reset 1 Reset input
TEMP 3 Temperature compensated refresh output from the HBM2E device.
Note: See also the Thermal Control section, in the Intel Agilex® 7 M-Series HBM2E Controller Details topic.
Cattrip 1 Catastrophic trip indication from the HBM2E device.
Note: See also the Thermal Control section, in the Intel Agilex® 7 M-Series HBM2E Controller Details topic.

The HBM2E IP for Intel Agilex® 7 M-Series devices supports only the Pseudo Channel mode of the HBM2E specification. Pseudo Channel mode includes the following features:

  • Pseudo-channel mode divides a single HBM2E channel into two individual subchannels of 64 bit I/O.
  • Both pseudo-channels share the channel’s row and column command bus, CK, and CKE inputs, but decode and execute commands individually.
  • Pseudo-channel mode requires an HBM burst length of 4.
  • Address BA4 directs commands to either pseudo-channel 0 (BA4 = 0) or pseudo-channel 1 (BA4 = 1). The HBM2E controller handles the addressing requirements of the pseudo-channels.
  • Power-down and self-refresh are common to both pseudo-channels, due to a shared CKE pin. Both pseudo-channels also share the channel’s mode registers.

User AXI Interface

Each Intel Agilex® 7 M-Series HBM2E interface supports a maximum of eight HBM2E channels. Each HBM2E channel has two AXI4 interfaces, one per Pseudo Channel. Each AXI4 interface includes 256-bit wide Write and Read Data AXI channels. The following figure shows the flow of data from user logic to the HBM2E DRAM through the UIBSS, while selecting HBM2E channels 0 and 7.

Figure 5.  Intel Agilex® 7 M-Series HBM2E Interface Using HBM2E Channels 0 through 7

The AXI4 protocol can handle concurrent writes and reads to the HBM2E controller. There is also a sideband user port per user channel pair, compliant to AXI4-Lite. The sideband provides access to user-controlled features such as ECC status, Power Down status, HBM2E temperature readout, calibration status, and User Interrupt configuration and status.

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