High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 4/21/2023

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6.2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Efficiency

The HBM2E controller provides high efficiency for any given address pattern from the user interface. The controller efficiently schedules incoming commands, avoiding frequent precharge and activate commands as well as frequent bus turn-around when possible.

Factors Affecting Controller Efficiency

Several factors can affect controller efficiency. For best efficiency, you should consider these factors in your design:

  • User-interface frequency vs HBM2E interface frequency - The frequency of user logic in the FPGA fabric plays an important role in determining HBM2E memory efficiency.
  • Controller Settings - The pseudo-BL8 mode helps to ensure shorter memory access timing between successive BL4 transactions, to improve controller efficiency. Also, BL4 transactions of AXI burst length 1 do not make efficient use of hard memory NoC bandwidth.
  • Traffic Patterns - Traffic patterns play an important role in determining controller efficiency.
    • Sequential vs random DRAM addresses: Sequential addresses enable the controller to issue consecutive write requests to an open page and help to achieve high controller efficiency. Random addresses require constant PRECHARGE/ACTIVATE commands and can reduce controller efficiency.
    • Set the User Auto Precharge Policy to FORCED and set the awuser[0]/aruser[0] signal on the AXI interface to HIGH to enable Auto Precharge for random transactions. For sequential transactions, set the Auto Precharge Policy to HINT.
    • Sequential Read only or Write Only transactions: Sequential read-only or write-only transactions see higher efficiency as they avoid bus turnaround times of the DRAM bi-directional data bus.
  • AXI Transaction IDs – Use of different AXI transaction IDs helps the HBM2E controller schedule the transactions for high efficiency. Use of the same AXI transaction ID preserves command order and may result in lower efficiency.
  • Temperature – There are two main temperature effects that reduce the bandwidth available for data transfers in the Intel Agilex® 7 HBM2E interface:
    • The HBM2E is exceeding a temperature threshold set in the General > Enable interface throttling based on temperature parameter.
    • Above 85°C, refreshes occur more frequently, so there is less bandwidth available for data transfers.
    The TEMP register value can be read back via the HBM2E controller's AXI4-Lite NoC target interface to help with the correlation of memory refreshes, temperature, and data bandwidth.