High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 4/21/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3. Address Mapping of the HBM2E Targets

You must assign a base address to each target that you connect to an initiator. The base address is a logical address that is your logic that uses that instance of the NoC Initiator IP.

Each initiator uses an independent 44-bit logical address space. The targets connected to HBM pseudo-channels are addressed using these 44-bit logical addresses. You must map the addresses for a given target in accordance with the following rules:

  • Each target has a fixed address span of 1 GB, regardless of the actual pseudo-channel capacity (512 MB for 4H and 1 GB for 8H devices). Hence, the base addresses should be aligned to 1 GB boundaries, implying that the least significant 30-bits of the base address must always be zero.
  • Targets must be mapped using non-overlapping address spaces.